• 1304 Citations
  • 18 h-Index
1982 …2020

Research output per year

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Research Output

  • 1304 Citations
  • 18 h-Index
  • 52 Conference contribution
  • 41 Article
  • 6 Conference article
  • 1 Paper
2020

A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in

Liu, K., Pu, H. & Shinohara, H., 2020 Mar, 2020 IEEE Custom Integrated Circuits Conference, CICC 2020. Institute of Electrical and Electronics Engineers Inc., 9075875. (Proceedings of the Custom Integrated Circuits Conference; vol. 2020-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 373-F 0.21%-Native-BER EE SRAM Physically Unclonable Function with 2-D Power-Gated Bit Cells and {V}_{\text{SS}} Bias-Based Dark-Bit Detection

Liu, K., Min, Y., Yang, X., Sun, H. & Shinohara, H., 2020 Jun, In : IEEE Journal of Solid-State Circuits. 55, 6, p. 1719-1732 14 p., 8957039.

Research output: Contribution to journalArticle

2019

A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

Wang, J. & Shinohara, H., 2019 Apr, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741737. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2018

A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

Liu, K., Min, Y., Yang, X., Sun, H. & Shinohara, H., 2018 Dec 14, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 161-164 4 p. 8579315. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

High-throughput von Neumann post-processing for random number generator

Zhang, R., Chen, S., Wan, C. & Shinohara, H., 2018 Jun 5, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
2017

Accurate nanopower supply-insensitive CMOS unit Vth extractor and α Vth extractor with continuous variety

Wang, J., Ding, L., Li, Q., Shinohara, H. & Inoue, Y., 2017 May 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 5, p. 1145-1155 11 p.

Research output: Contribution to journalArticle

Analysis and reduction of SRAM PUF Bit Error Rate

Shinohara, H., Zheng, B., Piao, Y., Liu, B. & Liu, S., 2017 Jun 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939688

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Correlation between static random access memory power-up state and transistor variation

Takeuchi, K., Mizutani, T., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 Apr 1, In : Japanese Journal of Applied Physics. 56, 4, 04CD03.

Research output: Contribution to journalArticle

7 Citations (Scopus)

Measurement of mismatch factor and noise of SRAM PUF using small bias voltage

Cui, Z., Zheng, B., Piao, Y., Liu, S., Xie, R. & Shinohara, H., 2017 Jun 20, 2017 International Conference of Microelectronic Test Structures, ICMTS 2017. Institute of Electrical and Electronics Engineers Inc., 7954264

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Measurement of static random access memory power-up state using an addressable cell array test structure

Takeuchi, K., Mizutani, T., Shinohara, H., Saraya, T., Kobayashi, M. & Hiramoto, T., 2017 Aug 1, In : IEEE Transactions on Semiconductor Manufacturing. 30, 3, p. 209-215 7 p., 7895199.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Mizutani, T., Takeuchi, K., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 Apr 1, In : Japanese Journal of Applied Physics. 56, 4, 04CD17.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2016

A 3.5 ppm/°C 0.85V bandgap reference circuit without resistors

Wang, J., Li, Q., Ding, L., Shinohara, H. & Inoue, Y., 2016 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1430-1437 8 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

AC direct multiple-string LED driver with low THD and minimum components

Yeh, Y., Chen, M., Li, X., Shinohara, H. & Yoshihara, T., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 117-118 2 p. 7401680

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

An output capacitor-less low dropout regulator with quick-responding circuits

Zhang, C., Mei, J., Shinohara, H. & Yoshihara, T., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 51-52 2 p. 7401635

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Design of a low-order sensorless controller by robust H∞ control for boost converters

Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 May 1, In : Journal of Power Electronics. 16, 3, p. 1025-1035 11 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Design of a Luenberger observer based sensorless multi-loop control for boost converters

Li, X., Chen, M., Shinohara, H. & Tsutomu, Y., 2016 Sep 7, International Conference on Electronics, Information, and Communications, ICEIC 2016. Institute of Electrical and Electronics Engineers Inc., 7563030

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Design of a sensorless controller synthesized by robust H∞ control for boost converters

Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 Feb 1, In : IEICE Transactions on Communications. E99B, 2, p. 356-363 8 p.

Research output: Contribution to journalArticle

Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure

Takeuchi, K., Mizutani, T., Saraya, T., Kobayashi, M., Hiramoto, T. & Shinohara, H., 2016 May 20, 2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-May. p. 130-134 5 p. 7476191

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)
2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. & 5 others, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014 Jan 1, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Mizutani, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N. & Hiramoto, T., 2014 Apr, In : Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04EC18.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Extremely low power digital and analog circuits

Shinohara, H., 2014 Jun, In : IEICE Transactions on Electronics. E97-C, 6, p. 469-475 7 p.

Research output: Contribution to journalArticle

Speed enhancement at Vdd = 0.4V and random Τpd variability reduction and analyisis of Τpd variability of silicon on thin buried oxide circuits

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K. & Yamaguchi, Y., 2014 Apr, In : Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04EC07.

Research output: Contribution to journalArticle

4 Citations (Scopus)
2013

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y. & 5 others, Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H. & Sakurai, T., 2013 Sep 9, 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. p. C36-C37 6576619. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y. & 5 others, Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H. & Sakurai, T., 2013 Sep 17, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. C36-C37 6578745. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

Yoshimoto, S., Miyano, S., Takamiya, M., Shinohara, H., Kawaguchi, H. & Yoshimoto, M., 2013 Nov 7, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 6658537. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Miyano, S., Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Sakurai, T. & Shinohara, H., 2013 Jan 29, In : IEEE Journal of Solid-State Circuits. 48, 4, p. 924-931 8 p., 6416957.

Research output: Contribution to journalArticle

11 Citations (Scopus)

Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013 May 15, In : IEEE Journal of Solid-State Circuits. 48, 8, p. 1986-1994 9 p., 6515395.

Research output: Contribution to journalArticle

6 Citations (Scopus)

Minimizing energy of integer unit by higher voltage flip-flop: V DDmin-aware dual supply voltage technique

Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 6, p. 1175-1179 5 p., 6236208.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Silicon on thin buried oxide (SOTB) technology for ultralow-power applications

Sugii, N., Iwamatsu, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Aono, H., Oda, H., Kamohara, S., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013 Oct 21, 2013 International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors, ULSIC vs. TFT 4. 1 ed. p. 189-196 8 p. (ECS Transactions; vol. 54, no. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K., Mizutani, T., Hiramoto, T. & Yamaguchi, Y., 2013 Dec 1, 2013 IEEE International Electron Devices Meeting, IEDM 2013. p. 33.2.1-33.2.4 6724742. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013 Sep 17, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. T212-T213 6578753. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013 Sep 9, 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. p. T212-T213 6576627. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Citations (Scopus)

Variation-aware subthreshold logic circuit design

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811842. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Vmin=0.4 v LSIs are the real with silicon-on-thin-buried-oxide (SOTB)-How is the application with 'Perpetuum-Mobile' micro-controller with SOTB?

Sugii, N., Iwamatsu, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Oda, H., Kamohara, S., Yamaguchi, Y., Ishibashi, K., Mizutani, T. & Hiramoto, T., 2013 Jan 1, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013. IEEE Computer Society, 6716576. (2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2012

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012 May 11, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. p. 486-487 2 p. 6177102. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 55).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits

Yasufuku, T., Hirairi, K., Pu, Y., Zheng, Y. F., Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M. & Sakurai, T., 2012 Jul 16, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 586-591 6 p. 6187553. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yamamoto, Y., Kawasumi, A., Moriwaki, S., Suzuki, T., Miyano, S. & Shinohara, H., 2012 Dec 14, 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. p. 317-320 4 p. 6341318. (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Miyano, S., Sakurai, T. & Shinohara, H., 2012, 2012 Symposium on VLSI Circuits, VLSIC 2012. p. 60-61 2 p. 6243789. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012 Nov 26, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012. 6330689. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012 Dec 1, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 12, p. 918-921 4 p., 6392909.

Research output: Contribution to journalArticle

6 Citations (Scopus)
2011

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 Sep 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 163-168 6 p. 5993630. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Muramatsu, A., Yasufuku, T., Nomura, M., Takamiya, M., Shinohara, H. & Sakurai, T., 2011 Dec 12, ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. p. 191-194 4 p. 6044897. (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Fuketa, H., Iida, S., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 Jan 1, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc., p. 984-989 6 p. 5981890. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Device-circuit interactions in extremely low voltage CMOS designs (invited)

Fuketa, H., Yasufuku, T., Iida, S., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 Dec 1, 2011 International Electron Devices Meeting, IEDM 2011. p. 25.1.1-25.1.4 6131609. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Post-silicon clock deskew employing hot-carrier injection trimming with on-chip skew monitoring and auto-stressing scheme for sub/near threshold digital circuits

Pu, Y., Zhang, X., Ikeuchi, K., Muramatsu, A., Kawasumi, A., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 May 1, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 58, 5, p. 294-298 5 p., 5772921.

Research output: Contribution to journalArticle

2010

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Suzuki, T., Moriwaki, S., Kawasumi, A., Miyano, S. & Shinohara, H., 2010 Dec 27, ESSCIRC 2010 - 36th European Solid State Circuits Conference. p. 354-357 4 p. 5619716. (ESSCIRC 2010 - 36th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)
5 Citations (Scopus)
2009

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y. & Shinohara, H., 2009 Nov 18, 2009 Symposium on VLSI Circuits. p. 158-159 2 p. 5205389. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Citations (Scopus)

Analysis technique for systematic variation over whole shot and wafer at 45 nm process node

Nakanishi, J., Notani, H., Nakase, Y. & Shinohara, H., 2009 Dec 1, ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. p. 585-588 4 p. 5351353. (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution