• 1304 Citations
  • 18 h-Index
1982 …2020

Research output per year

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Research Output

  • 1304 Citations
  • 18 h-Index
  • 52 Conference contribution
  • 41 Article
  • 6 Conference article
  • 1 Paper
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Article
2020

A 373-F 0.21%-Native-BER EE SRAM Physically Unclonable Function with 2-D Power-Gated Bit Cells and {V}_{\text{SS}} Bias-Based Dark-Bit Detection

Liu, K., Min, Y., Yang, X., Sun, H. & Shinohara, H., 2020 Jun, In : IEEE Journal of Solid-State Circuits. 55, 6, p. 1719-1732 14 p., 8957039.

Research output: Contribution to journalArticle

2017

Accurate nanopower supply-insensitive CMOS unit Vth extractor and α Vth extractor with continuous variety

Wang, J., Ding, L., Li, Q., Shinohara, H. & Inoue, Y., 2017 May 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 5, p. 1145-1155 11 p.

Research output: Contribution to journalArticle

Correlation between static random access memory power-up state and transistor variation

Takeuchi, K., Mizutani, T., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 Apr 1, In : Japanese Journal of Applied Physics. 56, 4, 04CD03.

Research output: Contribution to journalArticle

7 Citations (Scopus)

Measurement of static random access memory power-up state using an addressable cell array test structure

Takeuchi, K., Mizutani, T., Shinohara, H., Saraya, T., Kobayashi, M. & Hiramoto, T., 2017 Aug 1, In : IEEE Transactions on Semiconductor Manufacturing. 30, 3, p. 209-215 7 p., 7895199.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Mizutani, T., Takeuchi, K., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 Apr 1, In : Japanese Journal of Applied Physics. 56, 4, 04CD17.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2016

A 3.5 ppm/°C 0.85V bandgap reference circuit without resistors

Wang, J., Li, Q., Ding, L., Shinohara, H. & Inoue, Y., 2016 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1430-1437 8 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Design of a low-order sensorless controller by robust H∞ control for boost converters

Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 May 1, In : Journal of Power Electronics. 16, 3, p. 1025-1035 11 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Design of a sensorless controller synthesized by robust H∞ control for boost converters

Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 Feb 1, In : IEICE Transactions on Communications. E99B, 2, p. 356-363 8 p.

Research output: Contribution to journalArticle

2014

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Mizutani, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N. & Hiramoto, T., 2014 Apr, In : Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04EC18.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Extremely low power digital and analog circuits

Shinohara, H., 2014 Jun, In : IEICE Transactions on Electronics. E97-C, 6, p. 469-475 7 p.

Research output: Contribution to journalArticle

Speed enhancement at Vdd = 0.4V and random Τpd variability reduction and analyisis of Τpd variability of silicon on thin buried oxide circuits

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K. & Yamaguchi, Y., 2014 Apr, In : Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04EC07.

Research output: Contribution to journalArticle

4 Citations (Scopus)
2013

Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Miyano, S., Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Sakurai, T. & Shinohara, H., 2013 Jan 29, In : IEEE Journal of Solid-State Circuits. 48, 4, p. 924-931 8 p., 6416957.

Research output: Contribution to journalArticle

11 Citations (Scopus)

Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013 May 15, In : IEEE Journal of Solid-State Circuits. 48, 8, p. 1986-1994 9 p., 6515395.

Research output: Contribution to journalArticle

6 Citations (Scopus)

Minimizing energy of integer unit by higher voltage flip-flop: V DDmin-aware dual supply voltage technique

Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 6, p. 1175-1179 5 p., 6236208.

Research output: Contribution to journalArticle

3 Citations (Scopus)
2012

Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012 Dec 1, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 12, p. 918-921 4 p., 6392909.

Research output: Contribution to journalArticle

6 Citations (Scopus)
2011

Post-silicon clock deskew employing hot-carrier injection trimming with on-chip skew monitoring and auto-stressing scheme for sub/near threshold digital circuits

Pu, Y., Zhang, X., Ikeuchi, K., Muramatsu, A., Kawasumi, A., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 May 1, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 58, 5, p. 294-298 5 p., 5772921.

Research output: Contribution to journalArticle

2010
5 Citations (Scopus)
2009

Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

Nii, K., Tsukamoto, Y., Yabuuchi, M., Masuda, Y., Imaoka, S., Usui, K., Ohbayashi, S., Makino, H. & Shinohara, H., 2009 Mar 1, In : IEEE Journal of Solid-State Circuits. 44, 3, p. 977-986 10 p., 4787570.

Research output: Contribution to journalArticle

40 Citations (Scopus)
2008

A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2008 Jan 1, In : IEEE Journal of Solid-State Circuits. 43, 4, p. 938-943 6 p.

Research output: Contribution to journalArticle

27 Citations (Scopus)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2008, In : IEEE Journal of Solid-State Circuits. 43, 1, p. 180-191 12 p.

Research output: Contribution to journalArticle

47 Citations (Scopus)

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Okada, M., Ishii, A., Yoshihara, T., Makino, H., Ishibashi, K. & Shinohara, H., 2008, In : IEEE Journal of Solid-State Circuits. 43, 1, p. 96-108 13 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)

A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology

Fujii, M., Nii, K., Makino, H., Ohbayashi, S., Igarashi, M., Kawamura, T., Yokota, M., Tsuda, N., Yoshizawa, T., Tsutsui, T., Takeshita, N., Murata, N., Tanaka, T., Fujiwara, T., Asahina, K., Okada, M., Tomita, K., Takeuchl, M., Yamamoto, S., Sugimoto, H. & 1 others, Shinohara, H., 2008 Aug, In : IEICE Transactions on Electronics. E91-C, 8, p. 1338-1347 10 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Analytical model of static noise margin in CMOS SRAM for variation consideration

Shinohara, H., Nii, K. & Onodera, H., 2008 Sep, In : IEICE Transactions on Electronics. E91-C, 9, p. 1488-1500 13 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A robust silicon-on-insulator static-random-access-memory architecture by using advanced actively body-bias controlled technology

Hirano, Y., Tsujiuchi, M., Ishikawa, K., Shinohara, H., Terada, T., Maki, Y., Iwamatsu, T., Eikyu, K., Uchida, T., Obayashi, S., Nii, K., Tsukamoto, Y., Yabuuchi, M., Ipposhi, T., Oda, H. & Inoue, Y., 2008 Apr 18, In : Japanese journal of applied physics. 47, 4 PART 1, p. 2092-2096 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2007

A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K. & Shinohara, H., 2007 Apr 1, In : IEEE Journal of Solid-State Circuits. 42, 4, p. 820-829 10 p.

Research output: Contribution to journalArticle

86 Citations (Scopus)
1996

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

Ueda, K., Suzuki, H., Suda, K., Shinohara, H. & Mashiko, K., 1996 Jun 1, In : IEEE Journal of Solid-State Circuits. 31, 6, p. 810-817 8 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)

An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture

Makino, H., Nakase, Y., Suzuki, H., Morinaka, H., Shinohara, H. & Mashiko, K., 1996 Jun, In : IEEE Journal of Solid-State Circuits. 31, 6, p. 773-782 10 p.

Research output: Contribution to journalArticle

103 Citations (Scopus)
1992

A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Arima, Y., Murasaki, M., Yamada, T., Maeda, A. & Shinohara, H., 1992 Dec, In : IEEE Journal of Solid-State Circuits. 27, 12, p. 1854-1861 8 p.

Research output: Contribution to journalArticle

25 Citations (Scopus)
1991

A Flexible Multiport RAM Compiler for Data Path

Shinohara, H., Fujimori, K., Tsujihashi, Y., Kato, S., Horiba, Y., Matsumoto, N., Nakao, H. & Tada, A., 1991 Mar, In : IEEE Journal of Solid-State Circuits. 26, 3, p. 343-349 7 p.

Research output: Contribution to journalArticle

17 Citations (Scopus)
1990

A 24-b 50-ns Digital Image Signal Processor

Nakagawa, S. I., Matsumura, T., Segawa, H., Yoshimoto, M., Shinohara, H., Kato, S. I., Hatanaka, M. & Horiba, Y., 1990 Dec, In : IEEE Journal of Solid-State Circuits. 25, 6, p. 1484-1493 10 p.

Research output: Contribution to journalArticle

12 Citations (Scopus)
1987

A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

Wada, T., Hirose, T., Shinohara, H., Kawai, Y., Yuzuriha, K., Kohno, Y. & Kayano, S., 1987 Oct, In : IEEE Journal of Solid-State Circuits. 22, 5, p. 727-732 6 p.

Research output: Contribution to journalArticle

12 Citations (Scopus)

Submicrometer-Gate MOSFET's by the Use of Focused-Ion-Beam Exposure and a Dry Development Technique

Morimoto, H., Tsukamoto, K., Shinohara, H., Inuishi, M. & Kato, T., 1987 Feb, In : IEEE Transactions on Electron Devices. 34, 2, p. 230-234 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
1986

25-ns 256K ×1/64K × 4 CMOS SRAM's

Kayano, S., Ichinose, K., Kohno, Y., Shinohara, H., Anami, K., Murakami, S., Wada, T., Kawai, Y. & Akasaka, Y., 1986 Oct, In : IEEE Journal of Solid-State Circuits. 21, 5, p. 686-691 6 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)
1985

45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE.

Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y. & Kayano, S., 1985 Oct 1, In : IEEE Journal of Solid-State Circuits. SC-20, 5

Research output: Contribution to journalArticle

4 Citations (Scopus)

A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line

Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y. & Kayano, S., 1985, In : IEEE Journal of Solid-State Circuits. 20, 5, p. 929-934 6 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A Fast 8K x 8 Mixed CMOS Static RAM

Shinohara, H., Anami, K., Yoshihara, T., Kohno, Y., Akasaka, Y., Kayano, S. & Kihara, Y., 1985 Sep, In : IEEE Transactions on Electron Devices. 32, 9, p. 1792-1796 5 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
1983

A Divided Word-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM

Yoshimoto, M., Anami, K., Shinohara, H., Yoshihara, T., Takagi, H., Nagao, S., Rayano, S. & Nakano, T., 1983 Oct, In : IEEE Journal of Solid-State Circuits. 18, 5, p. 479-485 7 p.

Research output: Contribution to journalArticle

136 Citations (Scopus)

Analysis of parasitic resistance effects in MOS LSI

Anami, K., Yoshimoto, M., Shinohara, H., Tomisawa, O. & Nakano, T., 1983, In : Electronics and Communications in Japan (Part I: Communications). 66, 10, p. 106-113 8 p.

Research output: Contribution to journalArticle

Design Consideration of a Static Memory Cell

Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y. & Nakano, T., 1983 Aug, In : IEEE Journal of Solid-State Circuits. 18, 4, p. 414-418 5 p.

Research output: Contribution to journalArticle

31 Citations (Scopus)
1982

A 35 ns 16K NMOS Static RAM

Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y., Harada, H. & Nakano, T., 1982 Oct, In : IEEE Journal of Solid-State Circuits. 17, 5, p. 815-820 6 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)