• 267 Citations
  • 9 h-Index
19972020

Research output per year

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Research Output

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2020

Compiler software coherent control for embedded high performance multicore

Adhi, B. A., Kashimata, T., Takahashi, K., Kimura, K. & Kasahara, H., 2020 Mar 1, In : IEICE Transactions on Electronics. E103.C, 3, p. 85-97 13 p.

Research output: Contribution to journalArticle

Local memory mapping of multicore processors on an automatic parallelizing compiler

Oki, Y., Abe, Y., Yamamoto, K., Yamamoto, K., Shirakawa, T., Yoshida, A., Kimura, K. & Kasahara, H., 2020 Mar 1, In : IEICE Transactions on Electronics. E103.C, 3, p. 98-109 12 p.

Research output: Contribution to journalArticle

2019

Compiler-support for critical data persistence in NVM

Elkhouly, R., Alshboul, M., Hayashi, A., Solihin, Y. & Kimura, K., 2019 Dec, In : ACM Transactions on Architecture and Code Optimization. 16, 4, 54.

Research output: Contribution to journalArticle

Open Access

Efficient checkpointing with recompute scheme for non-volatile main memory

Alshboul, M., Elnawawy, H., Elkhouly, R., Kimura, K., Tuck, J. & Solihin, Y., 2019 May, In : ACM Transactions on Architecture and Code Optimization. 16, 2, 18.

Research output: Contribution to journalArticle

3 Citations (Scopus)
2016

Android video processing system combined with automatically parallelized and power optimized code by OSCAR compiler

Binh, B. D., Hirano, T., Mikami, H., Yamamoto, H., Kimura, K. & Kasahara, H., 2016, In : Journal of Information Processing. 24, 3, p. 504-511 8 p.

Research output: Contribution to journalArticle

2011

A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core

Nishii, O., Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Ishikawa, M., Yamada, T., Miyakoshi, J., Wada, Y., Kimura, K., Kasahara, H. & Maejima, H., 2011 Apr, In : IEICE Transactions on Electronics. E94-C, 4, p. 663-669 7 p.

Research output: Contribution to journalArticle

2008

Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

Shikano, H., Ito, M., Onouchi, M., Todaka, T., Tsunoda, T., Kodama, T., Uchiyama, K., Odaka, T., Kamei, T., Nagahama, E., Kusaoke, M., Nitta, Y., Wada, Y., Kimura, K. & Kasahara, H., 2008 Jan, In : IEEE Journal of Solid-State Circuits. 43, 4, p. 902-908 7 p.

Research output: Contribution to journalArticle

15 Citations (Scopus)

Power-aware compiler controllable chip multiprocessor

Shikano, H., Shirako, J., Wada, Y., Kimura, K. & Kasahara, H., 2008 Apr, In : IEICE Transactions on Electronics. E91-C, 4, p. 432-439 8 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2003

Multigrain parallel processing on compiler cooperative OSCAR chip multiprocessor architecture

Kimura, K., Kodaka, T., Obata, M. & Kasahara, H., 2003 Apr, In : IEICE Transactions on Electronics. E86-C, 4, p. 570-579 10 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP

Nakano, H., Ishizaka, K., Obata, M., Kimura, K. & Kasahara, H., 2003 Jun 1, In : International Journal of Parallel Programming. 31, 3, p. 211-223 13 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)