• 883 Citations
  • 15 h-Index
19982020

Research output per year

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Research Output

  • 883 Citations
  • 15 h-Index
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter
1998

High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Togawa, N., Hisaki, T., Yanagisawa, M. & Ohtsuki, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 265-274 10 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

1 Citation (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 519-526 8 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

4 Citations (Scopus)
7 Citations (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 125-128 4 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)
1999
1 Citation (Scopus)
16 Citations (Scopus)

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journalArticle

Fast motion estimation scheme for video coding using feature vector matching and motion vector's correlations

Zhao, T., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 67-82 16 p.

Research output: Contribution to journalArticle

2000
9 Citations (Scopus)

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. p. 544-547 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A high performance embedded wavelet video coder

Zhao, T., Yanagisawa, M. & Ohtsuki, T., 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 6, p. 979-986 8 p.

Research output: Contribution to journalArticle

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 309-312 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2001
1 Citation (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 156-161 6 p. 913297

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)
2002
3 Citations (Scopus)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., Vol. 1. p. 171-176 6 p. 1114930

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
2003

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

Shi, Y., Zhang, Z., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3056-3062 7 p.

Research output: Contribution to journalArticle

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journalArticle

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2003-January. p. 135-140 6 p. 1195006

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journalArticle

2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acoustic tracking of sperm whales using two sets of hydrophone array

Ura, T., Bahl, R., Sakata, M., Kojima, J., Fukuchi, T., Ura, J., Nose, Y., Sugimatsu, H., Mori, K., Nakatani, T. & Yanagisawa, M., 2004, 2004 International Symposium on Underwater Technology, UT'04 - Proceedings. p. 103-107 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asian Test Symposium. p. 432-437 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

An efficient algorithm/architecture codesign for image encoders

Choi, J., Togawa, N., Ikenaga, T., Goto, S., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 13-16 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 74-79 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 161-164 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

High-level power optimization based on thread partitioning

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

Research output: Contribution to journalArticle

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 743-750 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2005

A processor core synthesis system in IP-based SoC design

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. p. 286-291 6 p. 1466175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. Vol. 2005. p. 386-389 4 p. 1575460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

Research output: Contribution to journalArticle

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings - IEEE International Symposium on Circuits and Systems. p. 3499-3502 4 p. 1465383

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle