• 906 Citations
  • 15 h-Index
19982020

Research output per year

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Research Output

2n RRR: Improved stochastic number duplicator based on bit re-arrangement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Dec 10, 2018 New Generation of CAS, NGCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8572289

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

Sato, H., Yanagisawa, M. & Yoshimasu, T., 2017 Dec 1, EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January. p. 1-2 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

Shi, Y., Zhang, Z., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3056-3062 7 p.

Research output: Contribution to journalArticle

Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: Evaluation by large-scale real data

Takitoh, S., Fujii, S., Mase, Y., Takasaki, J., Yamazaki, T., Ohnishi, Y., Yanagisawa, M., Nakamura, Y. & Kamatani, N., 2007 Feb 15, In : Bioinformatics. 23, 4, p. 408-413 6 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 250-255. 6 p.

Research output: Contribution to conferencePaper

Acoustic tracking of sperm whales using two sets of hydrophone array

Ura, T., Bahl, R., Sakata, M., Kojima, J., Fukuchi, T., Ura, J., Nose, Y., Sugimatsu, H., Mori, K., Nakatani, T. & Yanagisawa, M., 2004 Dec 1, Proceedings of the 2004 International Symposium on UnderwaterTechnology, UT'04. p. 103-107 5 p. (2004 International Symposium on Underwater Technology, UT'04 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, Vol. 2016-May. p. 75-80 6 p. 7479179

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
5 Citations (Scopus)
1 Citation (Scopus)

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006 Jan 1, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 1083-1086 4 p. 5774956. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A fastweighted adder by reducing partial product for reconstruction in super-resolution

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012 Aug 17, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

Research output: Contribution to journalArticle

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journalArticle

12 Citations (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 244-247 4 p. 7032765. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Terada, K., Yanagisawa, M. & Togawa, N., 2015 Jul 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July. p. 2129-2132 4 p. 7169100

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Teradat, K., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 248-251 4 p. 7032766. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
16 Citations (Scopus)
9 Citations (Scopus)

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journalArticle

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, p. 544-547. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Jan 1, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 135-140 6 p. 1195006. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
11 Citations (Scopus)

A hardware-Trojan classification method utilizing boundary net structures

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Mar 26, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-4 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
1 Citation (Scopus)

A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A high performance embedded wavelet video coder

Zhao, T., Yanagisawa, M. & Ohtsuki, T., 2000 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 6, p. 979-986 8 p.

Research output: Contribution to journalArticle

A landmark-based route recommendation method for pedestrian walking strategies

Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
1 Citation (Scopus)

A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Kawamura, K., Yanagisawa, M. & Togawa, N., 2018 May 9, 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, Vol. 2018-March. p. 106-111 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A low cost and high speed CSD-based symmetric transpose block FIR implementation

Ye, J., Shi, Y., Togawa, N. & Yanagisawa, M., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 311-314 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
1 Citation (Scopus)

A low-power soft error tolerant latch scheme

Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec 1, Proceedings of the Asian Test Symposium, ATS'04. p. 432-437 6 p. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A multiple cyclic-route generation method for strolling based on point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, Vol. 2018-September. 8576185

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)