• 883 Citations
  • 15 h-Index
19982020

Research output per year

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Research Output

  • 883 Citations
  • 15 h-Index
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter

A multiple cyclic-route generation method with route length constraint considering point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

Research output: Contribution to journalArticle

An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons

Momose, R., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Dec 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January. p. 1-5 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)
3 Citations (Scopus)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., Vol. 1. p. 171-176 6 p. 1114930

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analysis of sperm whale click by MUSIC algorithm

Hirotsu, R., Ura, T., Bahl, R. & Yanagisawa, M., 2007, OCEANS 2006 - Asia Pacific. 4393900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 309-312 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)
1 Citation (Scopus)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 300-303 4 p. 7032779

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Sep 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 53-56 4 p. 8474263

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

An efficient algorithm/architecture codesign for image encoders

Choi, J., Togawa, N., Ikenaga, T., Goto, S., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
1 Citation (Scopus)

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. p. 576-579 4 p. 6272096

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices

Yokoyama, M., Koyama, R. & Yanagisawa, M., 2017 Jan 1, In : Journal of Sensors. 2017, 3980906.

Research output: Contribution to journalArticle

5 Citations (Scopus)

An FPGA implementation method based on distributed-register architectures

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

Research output: Contribution to journalArticle

Open Access

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 594-599 6 p. 1594750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An Ising model mapping to solve rectangle packing problem

Terada, K., Oku, D., Kanamaru, S., Tanaka, S., Hayashi, M., Yamaoka, M., Yanagisawa, M. & Togawa, N., 2018 Jun 5, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kawamura, K., Tanaka, S., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1736-1739 4 p. 6572200

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A processor core synthesis system in IP-based SoC design

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. p. 286-291 6 p. 1466175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, International System on Chip Conference. IEEE Computer Society, Vol. 2016-February. p. 7-12 6 p. 7406898

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A Proposal for Wearable Controller Device and Finger Gesture Recognition using Surface Electromyography

Tsuboi, A., Hirota, M., Sato, J., Yokoyama, M. & Yanagisawa, M., 2017 Nov 27, SIGGRAPH Asia 2017 Posters, SA 2017. Association for Computing Machinery, Inc, 9

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 156-161 6 p. 913297

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 13-16 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A robust scan-based side-channel attack method against HMAC-SHA-256 circuits

Oku, D., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, Vol. 2017-September. p. 79-84 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
1 Citation (Scopus)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark

Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journalArticle

30 Citations (Scopus)

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Apr 22, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-April. p. 465-470 6 p. 7092434

Research output: Chapter in Book/Report/Conference proceedingConference contribution

46 Citations (Scopus)

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

A selector-based FFT processor and its FPGA implementation

Hirai, Y., Kawamura, K., Yanagisawa, M. & Togawa, N., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 88-89 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journalArticle

A stayed location estimation method for sparse GPS positioning information

Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2017 Dec 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January. p. 1-5 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2 Citations (Scopus)
1 Citation (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 74-79 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A travel decision support algorithm: Landmark activity extraction from japanese travel comments

Bao, S., Yanagisawa, M. & Togawa, N., 2020 Jan 1, Studies in Computational Intelligence. Springer-Verlag, p. 109-123 15 p. (Studies in Computational Intelligence; vol. 849).

Research output: Chapter in Book/Report/Conference proceedingChapter

A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Apr 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-May. 8351058

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journalArticle

Autonomous recognition of bubble plumes for navigation of underwater robots in active shallow vent areas

Mizushima, H., Maki, T., Ura, T., Sakamaki, T., Kondo, H. & Yanagisawa, M., 2007, Oceans Conference Record (IEEE). 4449284

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)