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Research Output 1998 2020

  • 847 Citations
  • 14 h-Index
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter
2010
46 Citations (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 407-412 6 p. 5419848

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Networks (circuits)
Public key cryptography
Monitoring
47 Citations (Scopus)

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

Research output: Contribution to journalArticle

RSA Cryptosystem
Side Channel Attacks
Cryptography
Signature
Networks (circuits)
8 Citations (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Statistical methods
Hardware
Networks (circuits)
Side channel attack
1 Citation (Scopus)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Shi, Y., Tokumitsu, K., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1139-1142 4 p. 5774925

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
High definition television
Particle accelerators
Electric power utilization
Pixels
2009
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
30 Citations (Scopus)

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journalArticle

Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journalArticle

Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization
7 Citations (Scopus)

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec 15, Proceedings - International Test Conference. 5355900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Flip
Design
25 Citations (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 817-822 6 p. 4796581

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Data storage equipment
8 Citations (Scopus)
High-level Synthesis
Controllers
Floorplanning
Networks (circuits)
Controller

Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Sep, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

Research output: Contribution to journalArticle

Montgomery multiplication
Cryptography
Multiplier
Clocks
Time delay
Compaction
Masking
Unknown
Error detection
Masks
2008
3 Citations (Scopus)

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journalArticle

Cryptography
Failure analysis
Testing
Masking
Cost reduction
Masks
Compression
Unknown
2 Citations (Scopus)

Classification of sperm whale clicks and triangulation for real-time localization with SBL arrays

Hirotsu, R., Ura, T., Kojima, J., Sugimatsu, H., Bahl, R. & Yanagisawa, M., 2008, OCEANS 2008. 5151882

Research output: Chapter in Book/Report/Conference proceedingConference contribution

triangulation
Triangulation
whale
sperm
Ships
1 Citation (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 705-708 4 p. 4746121

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Decoding
Throughput
HIgh speed networks
Mobile devices
4 Citations (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 701-704 4 p. 4746120

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FIR filters
Engines
Digital storage
Specifications
Processing
8 Citations (Scopus)

Floorplan-driven high-level synthesis for distributed/shared-register architectures

Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug, In : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

Research output: Contribution to journalArticle

Scheduling
Networks (circuits)
High level synthesis
5 Citations (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data compression
Networks (circuits)
Cost reduction
Product design
Masks
9 Citations (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Networks (circuits)
High level synthesis
6 Citations (Scopus)

New correction algorithms for multiple comparisons in case-control multilocus association studies based on haplotypes and diplotype configurations

Misawa, K., Fujii, S., Yamazaki, T., Takahashi, A., Takasaki, J., Yanagisawa, M., Ohnishi, Y., Nakamura, Y. & Kamatani, N., 2008 Sep, In : Journal of Human Genetics. 53, 9, p. 789-801 13 p.

Research output: Contribution to journalArticle

Haplotypes
Linkage Disequilibrium
Genotype
Phenotype
Markov Chains
4 Citations (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Clocks
Time delay
Public key cryptography
Parallel architectures

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1779-1781 3 p. 4746386

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Masks
Degradation
2007
2 Citations (Scopus)

Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: Evaluation by large-scale real data

Takitoh, S., Fujii, S., Mase, Y., Takasaki, J., Yamazaki, T., Ohnishi, Y., Yanagisawa, M., Nakamura, Y. & Kamatani, N., 2007 Feb 15, In : Bioinformatics. 23, 4, p. 408-413 6 p.

Research output: Contribution to journalArticle

Single nucleotide Polymorphism
Nucleotides
Polymorphism
Clustering Methods
Single Nucleotide Polymorphism

Analysis of sperm whale click by MUSIC algorithm

Hirotsu, R., Ura, T., Bahl, R. & Yanagisawa, M., 2007, OCEANS 2006 - Asia Pacific. 4393900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Frequency estimation
White noise
3 Citations (Scopus)

Autonomous recognition of bubble plumes for navigation of underwater robots in active shallow vent areas

Mizushima, H., Maki, T., Ura, T., Sakamaki, T., Kondo, H. & Yanagisawa, M., 2007, Oceans Conference Record (IEEE). 4449284

Research output: Chapter in Book/Report/Conference proceedingConference contribution

autonomous underwater vehicle
navigation
bubble
plume
survey method
3 Citations (Scopus)

Design for secure test - A case study on pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2007, Proceedings - IEEE International Symposium on Circuits and Systems. p. 149-152 4 p. 4252593

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Hardware
Testing
Security of data
Data communication systems
6 Citations (Scopus)

Low altitude tracking of rugged seafloors for autonomous visual observation

Maki, T., Ura, T., Mizushima, H., Kondo, H., Sakamaki, T. & Yanagisawa, M., 2007, International Symposium on Underwater Technology, UT 2007 - International Workshop on Scientific Use of Submarine Cables and Related Technologies 2007. p. 488-494 7 p. 4231101

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Autonomous underwater vehicles
autonomous underwater vehicle
seafloor
Hazards
Sensors
17 Citations (Scopus)

Real time path-planning of an AUV based on characteristics of passive acoustic landmarks for visual mapping of shallow vent fields

Maki, T., Mizushima, H., Kondo, H., Ura, T., Sakamaki, T. & Yanagisawa, M., 2007, Oceans Conference Record (IEEE). 4449321

Research output: Chapter in Book/Report/Conference proceedingConference contribution

autonomous underwater vehicle
acoustics
bubble
plume
collision
2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle

Cryptography
Hardware
1 Citation (Scopus)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 594-599 6 p. 1594750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Networks (circuits)
Communication
Specifications
System-on-chip
14 Citations (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 653-658 6 p. 1594760

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cost reduction
Fans
Data compression
Product design
Costs
2 Citations (Scopus)

Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters

Zeng, G., Shi, Y., Takabatake, T., Yanagisawa, M. & Ito, H., 2006, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. p. 136-144 9 p. 4030924

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Automatic test pattern generation
Costs
Application specific integrated circuits
Hardware
Testing
2 Citations (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding
2005

A processor core synthesis system in IP-based SoC design

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. p. 286-291 6 p. 1466175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
System-on-chip
1 Citation (Scopus)

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journalArticle

Decomposition
17 Citations (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. Vol. 2005. p. 386-389 4 p. 1575460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Discrete Fourier transforms
Hardware

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

Research output: Contribution to journalArticle

Parallelism
Synthesis
Unit
Optimization
Timing

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings - IEEE International Symposium on Circuits and Systems. p. 3499-3502 4 p. 1465383

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Application programs
Data storage equipment
Hardware
6 Citations (Scopus)

Acoustic tracking of sperm whales using two sets of hydrophone array

Ura, T., Bahl, R., Sakata, M., Kojima, J., Fukuchi, T., Ura, J., Nose, Y., Sugimatsu, H., Mori, K., Nakatani, T. & Yanagisawa, M., 2004, 2004 International Symposium on Underwater Technology, UT'04 - Proceedings. p. 103-107 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hydrophones
Acoustics
Boats
Experiments
Acoustic waves
Hardware
Software
Unit
Application programs
Cycle
Data compression
Data Compression
Glossaries
Slice
Compression
2 Citations (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asian Test Symposium. p. 432-437 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coloring
Heuristic algorithms
Electric power utilization
System-on-chip
1 Citation (Scopus)

An efficient algorithm/architecture codesign for image encoders

Choi, J., Togawa, N., Ikenaga, T., Goto, S., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Motion estimation
Computational complexity
Bandwidth
Data storage equipment
4 Citations (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 13-16 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive systems
Hardware
Communication
Error correction
Throughput
Run Length
Data compression
Data Compression
Reconfiguration
Coding
4 Citations (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 74-79 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Clocks
Synchronization
High level synthesis

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 161-164 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electron energy levels
Clocks
Synchronization
Networks (circuits)
High level synthesis
2 Citations (Scopus)

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

Research output: Contribution to journalArticle

Error correction
Error Correction
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Reconfigurable Systems