• 906 Citations
  • 15 h-Index
19982020

Research output per year

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Research Output

2004

High-level power optimization based on thread partitioning

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

Research output: Contribution to journalArticle

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 743-750. 8 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec 1, In : Midwest Symposium on Circuits and Systems. 2, p. II445-II448

Research output: Contribution to journalConference article

1 Citation (Scopus)
2003

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

Shi, Y., Zhang, Z., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3056-3062 7 p.

Research output: Contribution to journalArticle

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journalArticle

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Jan 1, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 135-140 6 p. 1195006. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journalArticle

2002
3 Citations (Scopus)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., Vol. 1. p. 171-176 6 p. 1114930

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
2001
1 Citation (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001 Jan 1, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 156-161 6 p. 913297. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)
2000
9 Citations (Scopus)

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, p. 544-547. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

A high performance embedded wavelet video coder

Zhao, T., Yanagisawa, M. & Ohtsuki, T., 2000 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 6, p. 979-986 8 p.

Research output: Contribution to journalArticle

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 309-312 4 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
1999
1 Citation (Scopus)
16 Citations (Scopus)

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb 1, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journalArticle

Fast motion estimation scheme for video coding using feature vector matching and motion vector's correlations

Zhao, T., Yanagisawa, M. & Ohtsuki, T., 1999 Feb 1, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 67-82 16 p.

Research output: Contribution to journalArticle

1998

High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Togawa, N., Hisaki, T., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, p. 265-274. 10 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, p. 519-526. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)
7 Citations (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, p. 125-128 4 p. (IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)