• 926 Citations
  • 16 h-Index
19982020

Research output per year

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Research Output

Conference contribution

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 599-602 4 p. 6419106. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 407-412 6 p. 5419848. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Citations (Scopus)

Scan-based attack against Trivium stream cipher independent of scan structure

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811855. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Scan-based attack on the LED block cipher using scan signatures

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 Jan 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1460-1463 4 p. 6865421. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Sep 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 252-255 4 p. 7032767. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 555-558 4 p. 7032842. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Secure scan design with dynamically configurable connection

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 Jan 1, Proceedings - 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, PRDC 2013. IEEE Computer Society, p. 256-262 7 p. 6820873. (Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, p. 125-128 4 p. (IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Soft error tolerant latch designs with low power consumption (invited paper)

Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 52-55 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 607-610 4 p. 6419108. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs

Ye, J., Togawa, N., Yanagisawa, M. & Shi, Y., 2019 Jan 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702386. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Suspicious timing error prediction with in-cycle clock gating

Shi, Y., Igarashi, H., Togawa, N. & Yanagisawa, M., 2013 Jul 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 335-340 6 p. 6523631. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Throughput driven check point selection in suspicious timing error prediction based designs

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2014 Jan 1, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 6820280. (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050827

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Dec 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 1779-1781 3 p. 4746386. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Shi, Y., Tokumitsu, K., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Dec 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 1139-1142 4 p. 5774925. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 603-606 4 p. 6419107. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
Letter
Paper

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 250-255. 6 p.

Research output: Contribution to conferencePaper

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, p. 544-547. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012 Sep 28, p. 576-579. 4 p.

Research output: Contribution to conferencePaper

8 Citations (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004 Dec 1, p. 13-16. 4 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 74-79. 6 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec 1, p. 161-164. 4 p.

Research output: Contribution to conferencePaper

High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Togawa, N., Hisaki, T., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, p. 265-274. 10 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, p. 519-526. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 743-750. 8 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)