Masashi Tawada

講師(任期付)

  • 25 Citations
  • 3 h-Index
20112019
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Research Output 2011 2019

  • 25 Citations
  • 3 h-Index
  • 10 Conference contribution
  • 8 Article

Efficient Ising Model Mapping to Solving Slot Placement Problem

Kanamaru, S., Oku, D., Tawada, M., Tanaka, S., Hayashi, M., Yamaoka, M., Yanagisawa, M. & Togawa, N., 2019 Mar 6, 2019 IEEE International Conference on Consumer Electronics, ICCE 2019. Institute of Electrical and Electronics Engineers Inc., 8661947. (2019 IEEE International Conference on Consumer Electronics, ICCE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ising model
Combinatorial optimization
Hamiltonians
Electric wiring
Simulated annealing

2n RRR: Improved stochastic number duplicator based on bit re-arrangement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Dec 10, 2018 New Generation of CAS, NGCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8572289

Research output: Chapter in Book/Report/Conference proceedingConference contribution

flip-flops
Networks (circuits)
Flip flop circuits
output
Hyperbolic functions

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Sep 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 53-56 4 p. 8474263

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Composite materials
Mean square error
Artificial intelligence
Image processing
Error-correcting Codes
Data storage equipment
Systematic Error
Crosstalk
Error Correction
2 Citations (Scopus)
Rearrangement
Networks (circuits)
Logic circuits
Mean square error
Inaccurate