Masashi Tawada

次席研究員(研究院講師)

  • 37 Citations
  • 3 h-Index
20112020

Research output per year

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Research Output

  • 37 Citations
  • 3 h-Index
  • 17 Conference contribution
  • 9 Article
2020

A new LDPC code decoding method: Expanding the scope of ising machines

Tawada, M., Tanaka, S. & Togawa, N., 2020 Jan, 2020 IEEE International Conference on Consumer Electronics, ICCE 2020. Institute of Electrical and Electronics Engineers Inc., 9043057. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics; vol. 2020-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FPGA-based Heterogeneous Solver for Three-Dimensional Routing

Hasegawa, K., Ishikawa, R., Nishizawa, M., Kawamura, K., Tawada, M. & Togawa, N., 2020 Jan, ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 11-12 2 p. 9045660. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2020-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2020 Feb, 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020. Institute of Electrical and Electronics Engineers Inc., 9068967. (2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access
1 Citation (Scopus)
2019

Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder

Ideguchi, Y., Kamiya, N., Tawada, M. & Togawa, N., 2019 Aug, 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019. Institute of Electrical and Electronics Engineers Inc., p. 981-984 4 p. 8885174. (Midwest Symposium on Circuits and Systems; vol. 2019-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Efficient ising model mapping for induced subgraph isomorphism problems using ising machines

Yoshimura, N., Tawada, M., Tanaka, S., Arai, J., Yagi, S., Uchiyama, H. & Togawa, N., 2019 Sep, Proceedings - 2019 IEEE 9th International Conference on Consumer Electronics, ICCE-Berlin 2019. Velikic, G. & Gross, C. (eds.). IEEE Computer Society, p. 227-232 6 p. 8966218. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2019-September).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Efficient Ising Model Mapping to Solving Slot Placement Problem

Kanamaru, S., Oku, D., Tawada, M., Tanaka, S., Hayashi, M., Yamaoka, M., Yanagisawa, M. & Togawa, N., 2019 Mar 6, 2019 IEEE International Conference on Consumer Electronics, ICCE 2019. Institute of Electrical and Electronics Engineers Inc., 8661947. (2019 IEEE International Conference on Consumer Electronics, ICCE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Error Correction Coding of Stochastic Numbers Using BER Measurement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2019 Jul, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 243-246 4 p. 8854450. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Error correction system using stochastic numbers in symmetric channels and z channels

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2019 Nov, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., p. 578-581 4 p. 8965039. (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2018

2n RRR: Improved stochastic number duplicator based on bit re-arrangement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Dec 10, 2018 New Generation of CAS, NGCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8572289

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Sep 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 53-56 4 p. 8474263

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
5 Citations (Scopus)
2017

Effective write-reduction method for MLC non-volatile memory

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016
1 Citation (Scopus)

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Jan 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2015

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 304-307 4 p. 7032780. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
2 Citations (Scopus)
2 Citations (Scopus)

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, Vol. 9427. 94270K

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2013

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811826. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2011

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011 Aug 1, In : ieice electronics express. 8, 14, p. 1161-1167 7 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)