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Research Output 1994 2020

1994

Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 554-559 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
Maple
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
12 Citations (Scopus)
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1 Citation (Scopus)

Simultaneous placement and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994, Proceedings - IEEE International Symposium on Circuits and Systems. IEEE, Vol. 1. p. 483-486 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1995
2 Citations (Scopus)

Circuit partitioning algorithm with replication capability for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1995 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Replication
Field programmable gate arrays (FPGA)
Partitioning
Chip
1 Citation (Scopus)

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization

Togawa, N., Sato, M. & Ohtsuki, T., 1995, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, p. 319-327 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1996
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
Path
2 Citations (Scopus)

Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1996, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 294-297 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
3 Citations (Scopus)

Simultaneous placement and global routing for transport-processing FPGA layout

Togawa, N., Sato, M. & Ohtsuki, T., 1996, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Placement
Table lookup
Field programmable gate arrays (FPGA)
Layout
1997
3 Citations (Scopus)
Field Programmable Gate Array
Critical Path
Field programmable gate arrays (FPGA)
Partitioning
Path

A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1997 Oct, In : Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Networks (circuits)

Fast scheduling and allocation algorithms for entropy CODEC

Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

Research output: Contribution to journalArticle

Flow graphs
Entropy
Scheduling
Scheduling algorithms
Merging
5 Citations (Scopus)

Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 569-578 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
Processing
Delay circuits
1998
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
1 Citation (Scopus)

High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Togawa, N., Hisaki, T., Yanagisawa, M. & Ohtsuki, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 265-274 10 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Data flow graphs
Digital signal processing
Hardware
Computer hardware description languages
Scheduling
4 Citations (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 519-526 8 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Routing algorithms
Field programmable gate arrays (FPGA)
Specifications
7 Citations (Scopus)
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
3 Citations (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 125-128 4 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
1999
1 Citation (Scopus)
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
16 Citations (Scopus)
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journalArticle

Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
2000
9 Citations (Scopus)
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
1 Citation (Scopus)

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. p. 544-547 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital signal processors
Hardware
6 Citations (Scopus)

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 309-312 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Application programs
Flow control
Flow graphs
Computer hardware
1 Citation (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

Research output: Contribution to journalArticle

Associative storage
Synthesis
Application programs
Unit
Memory Function
2001
1 Citation (Scopus)
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors
6 Citations (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 156-161 6 p. 913297

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital signal processors
Hardware
Application programs
4 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journalArticle

Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
2002
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
3 Citations (Scopus)
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., Vol. 1. p. 171-176 6 p. 1114930

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
4 Citations (Scopus)
Power System
Power Consumption
Clocks
Electric power utilization
High-level Synthesis
4 Citations (Scopus)

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Motion estimation
Computer hardware description languages
Reconfigurable architectures
Computer hardware
Electric power utilization
2003

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journalArticle

Associative storage
Software System
Hardware
Application programs
Memory Function
2 Citations (Scopus)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journalArticle

Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
2 Citations (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2003-January. p. 135-140 6 p. 1195006

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Application programs

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journalArticle

Simulator
Simulators
Generator
Hardware
Application programs
2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Application programs
Data storage equipment
Hardware
Hardware
Software
Unit
Application programs
Cycle
2 Citations (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asian Test Symposium. p. 432-437 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coloring
Heuristic algorithms
Electric power utilization
System-on-chip
1 Citation (Scopus)

An efficient algorithm/architecture codesign for image encoders

Choi, J., Togawa, N., Ikenaga, T., Goto, S., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Motion estimation
Computational complexity
Bandwidth
Data storage equipment
4 Citations (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 13-16 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive systems
Hardware
Communication
Error correction
Throughput
4 Citations (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 74-79 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Clocks
Synchronization
High level synthesis

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 161-164 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electron energy levels
Clocks
Synchronization
Networks (circuits)
High level synthesis
2 Citations (Scopus)

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

Research output: Contribution to journalArticle

Error correction
Error Correction
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Reconfigurable Systems

High-level power optimization based on thread partitioning

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

Research output: Contribution to journalArticle

Thread
Partitioning
Optimization
Networks (circuits)
High-level Synthesis
3 Citations (Scopus)

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 743-750 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition