Nozomu Togawa

Research output

Research output per year 1994 2021

• 1057 Citations
• 16 h-Index
• 135 Conference contribution
• 106 Article
• 14 Paper
• 6 Conference article
• 9 More
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

Research output per year

Research output per year

Search results

• 2018

  Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Sep 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 97-102 6 p. 8474113. (2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Microcontrollers
  • Internet of things
  • Television
  • Sleep
  • Electric power utilization
  2 Citations (Scopus)

• Empirical evaluation and optimization of hardware-Trojan classification for gate-level netlists based on multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2320-2326 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Multilayer Neural Network
  • Hardware security
  • Hardware
  • Multilayer neural networks
  • Optimization

• Extension and performance/accuracy formulation for optimal GeAr-based approximate adder designs

  Hayamizu, K., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1014-1024 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Approximate Design
  • Adders
  • Gears
  • Formulation
  • Energy Consumption
  1 Citation (Scopus)

• Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

  Asai, D., Yanagisawa, M. & Togawa, N., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 64-67 4 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis
  • Energy harvesting
  • Networks (circuits)
  • Energy utilization
  • Scheduling

• Hardware trojan detection and classification based on logic testing utilizing steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2018 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2308-2319 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security
  • Hardware
  • Learning
  • Logic
  • Testing

• Hardware Trojan Detection Utilizing Machine Learning Approaches

  Hasegawa, K., Shi, Y. & Togawa, N., 2018 Sep 5, Proceedings - 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications and 12th IEEE International Conference on Big Data Science and Engineering, Trustcom/BigDataSE 2018. Institute of Electrical and Electronics Engineers Inc., p. 1891-1896 6 p. 8456155

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security
  • Machine Learning
  • Hardware
  • Machine learning
  • Outsourcing
  6 Citations (Scopus)

• Message from the Editor-in-Chief

  Togawa, N., 2018 Feb, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 1 1 p.

  Research output: Contribution to journal › Editorial › peer-review

• Personalized landmark recommendation algorithm based on language-specific satisfaction prediction using heterogeneous open data sources

  Bao, S., Yanagisawa, M. & Togawa, N., 2018 Aug, Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018. Akbar Hussain, D. M., Tomar, G. S. & Tomar, G. S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 70-76 7 p. 8864958. (Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Landmarks
  • Open Data
  • Recommendations
  • Prediction
  • Language

• Road-illuminance level inference across road networks based on Bayesian analysis

  Bao, S., Yanagisawa, M. & Togawa, N., 2018 Mar 26, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Machine learning

• Robust AES circuit design for delay variation using suspicious timing error prediction

  Yahagi, Y., Yanagisawa, M. & Togawa, N., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 101-102 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Cryptography
  • Networks (circuits)
  • Timing circuits

• Robust indoor/outdoor detection method based on sparse GPS positioning information

  Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 8576188. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2018-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Global positioning system
  • Classifiers
  • Machine learning
  • Experiments
  3 Citations (Scopus)

• Scan-based side-channel attack against HMAC-SHA-256 circuits based on isolating bit-transition groups using scan signatures

  Oku, D., Yanagisawa, M. & Togawa, N., 2018 Feb, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 16-28 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Side channel attack
  • Networks (circuits)
  1 Citation (Scopus)

• Soft error tolerant latch designs with low power consumption (invited paper)

  Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 52-55 4 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Electric power utilization
  • Semiconductor materials
  • Radiation
  • Electric potential
  2 Citations (Scopus)

• Stochastic number duplicators based on bit re-arrangement using randomized bit streams

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Rearrangement
  • Logic circuits
  • Networks (circuits)
  • Mean square error
  • Experimental Evaluation
  5 Citations (Scopus)
• 2017

  A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • High level synthesis
  • Architecture
  • Controller
  • Controllers

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • Leakage
  • High level synthesis
  • Bias voltage
  • Compensation and Redress

• A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security
  • Hardware
  • Machine Learning
  • Machine learning
  • Support Vector Machine
  14 Citations (Scopus)

• An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons

  Momose, R., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Dec 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January. p. 1-5 5 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • beacons
  • Bluetooth
  • positioning
  • proximity
  • filters
  8 Citations (Scopus)

• A robust scan-based side-channel attack method against HMAC-SHA-256 circuits

  Oku, D., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, p. 79-84 6 p. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2017-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Side channel attack
  • Networks (circuits)
  1 Citation (Scopus)

• A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

  Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Nov 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Landmarks
  • Lighting
  • Safety
  • Count
  • Algorithm Design
  3 Citations (Scopus)

• A stayed location estimation method for sparse GPS positioning information

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2017 Dec 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January. p. 1-5 5 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • positioning
  • Global positioning system
  • Mobile computing
  • electric batteries
  • intervals
  1 Citation (Scopus)

• Effective write-reduction method for MLC non-volatile memory

  Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699. (Proceedings - IEEE International Symposium on Circuits and Systems).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data storage equipment
  • Durability
  • Embedded systems

• Efficient multiplexer networks for field-data extractors and their evaluations

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 Apr, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Extractor
  • Wire
  • Evaluation
  • Networks (circuits)
  • Output

• Hardware Trojan detection and classification based on steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225. (2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security
  • Testing
  • Networks (circuits)
  1 Citation (Scopus)

• Hardware Trojans classification for gate-level netlists using multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227. (2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security
  • Multilayer neural networks
  • Integrated circuit design
  • Outsourcing
  • Machine learning
  36 Citations (Scopus)

• Implementation evaluation of scan-based attack against a Trivium cipher circuit

  Oku, D., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 220-223 4 p. 7803938. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field programmable gate arrays (FPGA)
  • Networks (circuits)

• Indoor navigation based on real-Time direction information generation using wearable glasses

  Iwanaji, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 7804754

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • navigation
  • Navigation systems
  • Glass
  • Navigation
  • landmarks
  2 Citations (Scopus)

• Message from the editor-in-chief

  Togawa, N., 2017 Feb, In: IPSJ Transactions on System LSI Design Methodology. 10, p. 1 1 p.

  Research output: Contribution to journal › Editorial › peer-review

• Personalized one-day travel with multi-nearby-landmark recommendation

  Bao, S., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, p. 239-242 4 p. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2017-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Planning
  • Industry
  1 Citation (Scopus)

• Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050827

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security
  • Feature extraction
  • Classifiers
  • Integrated circuit design
  • Machine learning
  35 Citations (Scopus)

• Trojan-net feature extraction and its application to hardware-Trojan detection for gate-level netlists using random forest

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2857-2868 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Feature Extraction
  • Random Forest
  • Hardware security
  • Hardware
  • Feature extraction
  4 Citations (Scopus)
• 2016

  A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Code Generation
  • Error-correcting Codes
  • Clustering
  • Data storage equipment
  • Crosstalk
  1 Citation (Scopus)

• A delay variation and floorplan aware high-level synthesis algorithm with body biasing

  Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, p. 75-80 6 p. 7479179. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2016-May).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis
  • Bias voltage
  • Degradation
  • Networks (circuits)
  1 Citation (Scopus)

• A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis
  • clocks
  • Clocks
  • Field programmable gate arrays (FPGA)
  • synthesis
  3 Citations (Scopus)

• A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

  Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

  Research output: Contribution to journal › Article › peer-review

  • Internet of things
  • Power Consumption
  • Power Analysis
  • Energy Consumption
  • Noise Reduction
  1 Citation (Scopus)

• A high-performance circuit design algorithm using data dependent approximation

  Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Networks (circuits)
  • approximation
  • adding circuits
  • performance
  • Adders

• A landmark-based route recommendation method for pedestrian walking strategies

  Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks
  • Pedestrians
  • walking
  • recommendations
  • Walking
  3 Citations (Scopus)

• A low-power soft error tolerant latch scheme

  Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Electric power utilization
  • Integrated circuits
  • Capacitance
  • Networks (circuits)
  • Electric potential
  1 Citation (Scopus)

• A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

  Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. Buchner, T., Zhao, D., Bhatia, K. & Sridhar, R. (eds.). IEEE Computer Society, p. 7-12 6 p. 7406898. (International System on Chip Conference; vol. 2016-February).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis
  • Scheduling
  2 Citations (Scopus)

• A safe and comprehensive route finding method for pedestrian based on lighting and landmark

  Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks
  • illuminating
  • routes
  • Lighting
  • fear
  6 Citations (Scopus)

• A visible corner-landmark based route finding algorithm for pedestrian navigation

  Takeda, K., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 601-602 2 p. 7398498

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks
  • Pedestrians
  • navigation
  • routes
  • Navigation
  3 Citations (Scopus)

• Bi-partitioning based multiplexer network for field-data extractors

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Jul, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

  Research output: Contribution to journal › Article › peer-review

  • Extractor
  • Partitioning
  • Stream Processing
  • Experimental Results
  • Consecutive
  1 Citation (Scopus)

• Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Jan 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data storage equipment
  • Crosstalk
  • Radiation
  • Energy utilization
  2 Citations (Scopus)

• Clock skew estimate modeling for FPGA high-level synthesis and its application

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis
  • Clocks
  • Field programmable gate arrays (FPGA)
  • Computer simulation
  • Networks (circuits)
  3 Citations (Scopus)

• Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

  Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks
  • routes
  • wrist
  • Information services
  • partitions
  2 Citations (Scopus)

• From the EDA perspective

  Togawa, N., 2016 Sep 1, In: Journal of the Institute of Electronics, Information and Communication Engineers. 99, 9, p. 901-906 6 p.

  Research output: Contribution to journal › Review article › peer-review

• Hardware Trojans classification for gate-level netlists based on machine learning

  Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security
  • Machine learning
  • Support vector machines
  • Classifiers
  40 Citations (Scopus)

• Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

  Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Quantitative Evaluation
  • Hardware security
  • Pattern Matching
  • Hardware
  • Pattern matching
  9 Citations (Scopus)

• Hash-Table and balanced-Tree based fib architecture for ccn routers

  Shimazaki, K., Aoki, T., Hatano, T., Otsuka, T., Miyazaki, A., Tsuda, T. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 67-68 2 p. 7799736. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Routers
  • Next generation networks
  • data structures
  • entry
  • Data structures
  1 Citation (Scopus)

• Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

  Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field programmable gate arrays (FPGA)
  • Networks (circuits)
  • Pixels
  • Delay circuits
  • Data storage equipment
  2 Citations (Scopus)