Nozomu Togawa

Research output

Research output per year 1994 2021

• 1139 Citations
• 16 h-Index
• 139 Conference contribution
• 109 Article
• 14 Paper
• 6 Conference article
• 9 More
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

Research output per year

Research output per year

Search results

• 2018

  A selector-based FFT processor and its FPGA implementation

  Hirai, Y., Kawamura, K., Yanagisawa, M. & Togawa, N., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 88-89 2 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Fast Fourier transforms 100%
  • Field programmable gate arrays (FPGA) 85%
  • Signal processing 12%

• A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 May 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Location Estimation 100%
  • Positioning 83%
  • Global positioning system 52%
  • Mobile Devices 18%
  • Battery 14%
  2 Citations (Scopus)

• A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Apr 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8351058. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2018-May).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field programmable gate arrays (FPGA) 100%
  • Networks (circuits) 67%
  • Hardware security 34%
  • Computer hardware 31%
  • Reconfigurable hardware 18%

• Bicycle behavior recognition using sensors equipped with smartphone

  Usami, Y., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 8576254. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2018-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Bicycles 100%
  • Smartphones 80%
  • Sensors 44%
  • Accidents 11%
  • Machine learning 10%
  1 Citation (Scopus)

• Designing subspecies of hardware trojans and their detection using neural network approach

  Inoue, T., Hasegawa, K., Kobayashi, Y., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 8576247. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2018-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security 100%
  • Neural networks 47%
  • Computer hardware 30%
  • Trigger circuits 20%
  • Domestic appliances 15%
  3 Citations (Scopus)

• Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Sep 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 97-102 6 p. 8474113. (2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Microcontrollers 100%
  • Internet of things 34%
  • Television 22%
  • Sleep 21%
  • Electric power utilization 15%
  2 Citations (Scopus)

• Empirical evaluation and optimization of hardware-Trojan classification for gate-level netlists based on multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2320-2326 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Multilayer Neural Network 100%
  • Hardware security 78%
  • Hardware 74%
  • Multilayer neural networks 62%
  • Optimization 46%
  2 Citations (Scopus)

• Extension and performance/accuracy formulation for optimal GeAr-based approximate adder designs

  Hayamizu, K., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1014-1024 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Approximate Design 100%
  • Adders 72%
  • Gears 57%
  • Formulation 41%
  • Energy Consumption 40%
  1 Citation (Scopus)

• Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

  Asai, D., Yanagisawa, M. & Togawa, N., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 64-67 4 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis 100%
  • Energy harvesting 79%
  • Networks (circuits) 14%
  • Energy utilization 9%
  • Scheduling 8%

• Hardware trojan detection and classification based on logic testing utilizing steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2018 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2308-2319 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security 100%
  • Hardware 95%
  • Learning 71%
  • Logic 61%
  • Testing 55%

• Hardware Trojan Detection Utilizing Machine Learning Approaches

  Hasegawa, K., Shi, Y. & Togawa, N., 2018 Sep 5, Proceedings - 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications and 12th IEEE International Conference on Big Data Science and Engineering, Trustcom/BigDataSE 2018. Institute of Electrical and Electronics Engineers Inc., p. 1891-1896 6 p. 8456155

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Machine Learning 100%
  • Hardware security 97%
  • Hardware 75%
  • Machine learning 55%
  • Outsourcing 14%
  6 Citations (Scopus)

• Message from the Editor-in-Chief

  Togawa, N., 2018 Feb, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 1 1 p.

  Research output: Contribution to journal › Editorial › peer-review

• Personalized landmark recommendation algorithm based on language-specific satisfaction prediction using heterogeneous open data sources

  Bao, S., Yanagisawa, M. & Togawa, N., 2018 Aug, Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018. Akbar Hussain, D. M., Tomar, G. S. & Tomar, G. S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 70-76 7 p. 8864958. (Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Landmarks 100%
  • Open Data 93%
  • Recommendations 81%
  • Prediction 60%
  • Language 55%

• Road-illuminance level inference across road networks based on Bayesian analysis

  Bao, S., Yanagisawa, M. & Togawa, N., 2018 Mar 26, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. Mohanty, S. P., Corcoran, P., Li, H., Sengupta, A. & Lee, J-H. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. (2018 IEEE International Conference on Consumer Electronics, ICCE 2018; vol. 2018-January).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Machine learning 100%

• Robust AES circuit design for delay variation using suspicious timing error prediction

  Yahagi, Y., Yanagisawa, M. & Togawa, N., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 101-102 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Cryptography 100%
  • Error 91%
  • Networks (circuits) 66%
  • Timing circuits 26%
  • Simulation 15%

• Robust indoor/outdoor detection method based on sparse GPS positioning information

  Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 8576188. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2018-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Global positioning system 100%
  • Random forests 61%
  • Classifiers 41%
  • Machine learning 21%
  • Experiments 10%
  3 Citations (Scopus)

• Scan-based side-channel attack against HMAC-SHA-256 circuits based on isolating bit-transition groups using scan signatures

  Oku, D., Yanagisawa, M. & Togawa, N., 2018 Feb, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 16-28 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Side channel attack 100%
  • Networks (circuits) 44%
  2 Citations (Scopus)

• Stochastic number duplicators based on bit re-arrangement using randomized bit streams

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Rearrangement 100%
  • Logic circuits 21%
  • Networks (circuits) 20%
  • Mean square error 17%
  • Experimental Evaluation 16%
  5 Citations (Scopus)
• 2017

  A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 48%
  • Controllers 27%

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • Leakage 66%
  • High level synthesis 64%
  • Bias voltage 63%
  • Compensation and Redress 38%

• A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security 100%
  • Hardware 95%
  • Machine Learning 85%
  • Machine learning 57%
  • Support Vector Machine 32%
  16 Citations (Scopus)

• A low cost and high speed CSD-based symmetric transpose block FIR implementation

  Ye, J., Shi, Y., Togawa, N. & Yanagisawa, M., 2017 Jul 1, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Qin, Y., Hong, Z. & Tang, T-A. (eds.). IEEE Computer Society, p. 311-314 4 p. (Proceedings of International Conference on ASIC; vol. 2017-October).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Costs 100%
  • Reusability 98%
  • Digital signal processing 89%
  • Energy utilization 61%
  5 Citations (Scopus)

• An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons

  Momose, R., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Dec 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January. p. 1-5 5 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • beacons 100%
  • Bluetooth 77%
  • positioning 73%
  • proximity 69%
  • filters 52%
  8 Citations (Scopus)

• A robust scan-based side-channel attack method against HMAC-SHA-256 circuits

  Oku, D., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, p. 79-84 6 p. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2017-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Side channel attack 100%
  • Networks (circuits) 44%
  3 Citations (Scopus)

• A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

  Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Nov 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Landmarks 100%
  • Lighting 60%
  • Safety 34%
  • Count 26%
  • Algorithm Design 20%
  3 Citations (Scopus)

• A stayed location estimation method for sparse GPS positioning information

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2017 Dec 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-5 5 p. (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; vol. 2017-January).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • positioning 100%
  • Global positioning system 86%
  • Mobile computing 16%
  • electric batteries 14%
  • intervals 10%
  1 Citation (Scopus)

• Designing hardware trojans and their detection based on a SVM-based approach

  Inoue, T., Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Qin, Y., Hong, Z. & Tang, T-A. (eds.). IEEE Computer Society, p. 811-814 4 p. (Proceedings of International Conference on ASIC; vol. 2017-October).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security 100%
  • Support vector machines 62%
  • Machine learning 14%
  • Classifiers 13%
  • Computer hardware 11%
  17 Citations (Scopus)

• Effective write-reduction method for MLC non-volatile memory

  Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699. (Proceedings - IEEE International Symposium on Circuits and Systems).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data storage equipment 100%
  • Durability 33%
  • Embedded systems 19%

• Efficient multiplexer networks for field-data extractors and their evaluations

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 Apr, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Extractor 100%
  • Wire 54%
  • Evaluation 52%
  • Networks (circuits) 19%
  • Output 19%

• Hardware Trojan detection and classification based on steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225. (2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security 100%
  • Testing 40%
  • Networks (circuits) 21%
  1 Citation (Scopus)

• Hardware Trojans classification for gate-level netlists using multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227. (2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security 100%
  • Multilayer neural networks 80%
  • Integrated circuit design 47%
  • Outsourcing 23%
  • Machine learning 14%
  42 Citations (Scopus)

• Implementation evaluation of scan-based attack against a Trivium cipher circuit

  Oku, D., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 220-223 4 p. 7803938. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field programmable gate arrays (FPGA) 100%
  • Networks (circuits) 67%

• Indoor navigation based on real-Time direction information generation using wearable glasses

  Iwanaji, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 7804754

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • navigation 100%
  • Navigation systems 80%
  • Glass 64%
  • Navigation 61%
  • landmarks 56%
  2 Citations (Scopus)

• Message from the editor-in-chief

  Togawa, N., 2017 Feb, In: IPSJ Transactions on System LSI Design Methodology. 10, p. 1 1 p.

  Research output: Contribution to journal › Editorial › peer-review

• Personalized one-day travel with multi-nearby-landmark recommendation

  Bao, S., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, p. 239-242 4 p. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; vol. 2017-September).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Planning 100%
  • Industry 34%
  1 Citation (Scopus)

• Soft error tolerant latch designs with low power consumption (invited paper)

  Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2017 Jul 1, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Qin, Y., Hong, Z. & Tang, T-A. (eds.). IEEE Computer Society, p. 52-55 4 p. (Proceedings of International Conference on ASIC; vol. 2017-October).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Electric power utilization 100%
  • Semiconductor materials 15%
  • Radiation 13%
  • Electric potential 8%
  2 Citations (Scopus)

• Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050827

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Hardware security 100%
  • Random forests 82%
  • Feature extraction 60%
  • Classifiers 55%
  • Integrated circuit design 47%
  43 Citations (Scopus)

• Trojan-net feature extraction and its application to hardware-Trojan detection for gate-level netlists using random forest

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2857-2868 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Feature Extraction 100%
  • Random Forest 97%
  • Hardware security 85%
  • Hardware 81%
  • Random forests 70%
  4 Citations (Scopus)
• 2016

  A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Code Generation 100%
  • Error-correcting Codes 67%
  • Clustering 54%
  • Data storage equipment 34%
  • Crosstalk 15%
  1 Citation (Scopus)

• A delay variation and floorplan aware high-level synthesis algorithm with body biasing

  Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, p. 75-80 6 p. 7479179. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2016-May).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis 100%
  • Bias voltage 65%
  • Degradation 18%
  • Networks (circuits) 14%
  1 Citation (Scopus)

• A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis 100%
  • clocks 78%
  • Clocks 66%
  • Field programmable gate arrays (FPGA) 63%
  • synthesis 56%
  3 Citations (Scopus)

• A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

  Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

  Research output: Contribution to journal › Article › peer-review

  • Internet of things 100%
  • Power Consumption 77%
  • Power Analysis 66%
  • Energy Consumption 36%
  • Electric power utilization 35%
  1 Citation (Scopus)

• A high-performance circuit design algorithm using data dependent approximation

  Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Networks (circuits) 100%
  • approximation 95%
  • adding circuits 94%
  • performance 80%
  • Adders 66%

• A landmark-based route recommendation method for pedestrian walking strategies

  Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks 100%
  • Pedestrians 95%
  • walking 92%
  • recommendations 75%
  • Walking 62%
  3 Citations (Scopus)

• A low-power soft error tolerant latch scheme

  Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Electric power utilization 100%
  • Integrated circuits 41%
  • Capacitance 38%
  • Networks (circuits) 24%
  • Electric potential 23%
  1 Citation (Scopus)

• A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

  Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. Buchner, T., Zhao, D., Bhatia, K. & Sridhar, R. (eds.). IEEE Computer Society, p. 7-12 6 p. 7406898. (International System on Chip Conference; vol. 2016-February).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High level synthesis 100%
  • Scheduling 26%
  2 Citations (Scopus)

• A safe and comprehensive route finding method for pedestrian based on lighting and landmark

  Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks 100%
  • illuminating 70%
  • routes 59%
  • Lighting 57%
  • fear 36%
  7 Citations (Scopus)

• A visible corner-landmark based route finding algorithm for pedestrian navigation

  Takeda, K., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 601-602 2 p. 7398498

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • landmarks 100%
  • Pedestrians 95%
  • navigation 88%
  • routes 59%
  • Navigation 54%
  3 Citations (Scopus)

• Bi-partitioning based multiplexer network for field-data extractors

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Jul, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

  Research output: Contribution to journal › Article › peer-review

  • Extractor 100%
  • Partitioning 71%
  • Stream Processing 32%
  • Experimental Results 18%
  • Count 15%
  1 Citation (Scopus)

• Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Jan 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data storage equipment 100%
  • Crosstalk 15%
  • Radiation 10%
  • Energy utilization 9%
  2 Citations (Scopus)