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Research Output 1994 2020

2017
Extractor
Wire
Evaluation
Networks (circuits)
Partitioning
1 Citation (Scopus)

Hardware Trojan detection and classification based on steady state learning

Oya, M., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Networks (circuits)
Hardware security
19 Citations (Scopus)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multilayer neural networks
Hardware
Outsourcing
Learning systems
Integrated circuit design

Implementation evaluation of scan-based attack against a Trivium cipher circuit

Oku, D., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 220-223 4 p. 7803938

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
Processing
2 Citations (Scopus)

Indoor navigation based on real-Time direction information generation using wearable glasses

Iwanaji, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 7804754

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Navigation systems
navigation
Navigation
Glass
landmarks

Message from the editor-in-chief

Togawa, N., 2017 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 10, p. 1 1 p.

Research output: Contribution to journalEditorial

Personalized one-day travel with multi-nearby-landmark recommendation

Bao, S., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, Vol. 2017-September. p. 239-242 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Planning
Industry
1 Citation (Scopus)

Rotator-based multiplexer network synthesis for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 Apr 19, Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. IEEE Computer Society, p. 194-199 6 p. 7905464

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wire
16 Citations (Scopus)

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050827

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Feature extraction
Classifiers
Learning systems
Outsourcing
Hardware
2 Citations (Scopus)
Random Forest
Feature Extraction
Learning systems
Feature extraction
Hardware
2016
1 Citation (Scopus)
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many
1 Citation (Scopus)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, Vol. 2016-May. p. 75-80 6 p. 7479179

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bias voltage
Degradation
Networks (circuits)
High level synthesis
3 Citations (Scopus)

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547

Research output: Chapter in Book/Report/Conference proceedingConference contribution

clocks
Field programmable gate arrays (FPGA)
Clocks
synthesis
Networks (circuits)

A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

Research output: Contribution to journalArticle

Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
approximation
adding circuits
Adders
time measurement
3 Citations (Scopus)

A landmark-based route recommendation method for pedestrian walking strategies

Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
walking
recommendations
Walking
routes
1 Citation (Scopus)

A low-power soft error tolerant latch scheme

Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Integrated circuits
Capacitance
Networks (circuits)
Electric potential
2 Citations (Scopus)

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, International System on Chip Conference. IEEE Computer Society, Vol. 2016-February. p. 7-12 6 p. 7406898

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
High level synthesis
3 Citations (Scopus)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark

Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
illuminating
Lighting
routes
fear
1 Citation (Scopus)

A visible corner-landmark based route finding algorithm for pedestrian navigation

Takeda, K., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 601-602 2 p. 7398498

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
navigation
Navigation
routes
Visibility
1 Citation (Scopus)
Extractor
Partitioning
Stream Processing
Consecutive
Count
2 Citations (Scopus)

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Jan 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Code generation
Crosstalk
Energy utilization
Radiation
3 Citations (Scopus)

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Clocks
High level synthesis
Networks (circuits)
1 Citation (Scopus)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
routes
wrist
Information services
partitions
1 Citation (Scopus)

Effective parallel algorithm for GPGPU-accelerated explicit routing optimization

Kikuta, K., Oki, E., Yamanaka, N., Togawa, N. & Nakazato, H., 2016 Feb 23, 2015 IEEE Global Communications Conference, GLOBECOM 2015. Institute of Electrical and Electronics Engineers Inc., 7416979

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer programming
Parallel algorithms
programming
Program processors
Genetic algorithms

From the EDA perspective

Togawa, N., 2016 Sep 1, In : Journal of the Institute of Electronics, Information and Communication Engineers. 99, 9, p. 901-906 6 p.

Research output: Contribution to journalReview article

22 Citations (Scopus)

Hardware Trojans classification for gate-level netlists based on machine learning

Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Support vector machines
Learning systems
Hardware
Classifiers
Hardware security
6 Citations (Scopus)

Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

Research output: Contribution to journalArticle

Quantitative Evaluation
Pattern matching
Pattern Matching
Hardware
Benchmark
1 Citation (Scopus)

Hash-Table and balanced-Tree based fib architecture for ccn routers

Shimazaki, K., Aoki, T., Hatano, T., Otsuka, T., Miyazaki, A., Tsuda, T. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 67-68 2 p. 7799736

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Next generation networks
data structures
Data structures
Servers
2 Citations (Scopus)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
Pixels
Delay circuits
Data storage equipment

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Monitoring
4 Citations (Scopus)

In-situ Trojan authentication for invalidating hardware-Trojan functions

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, Vol. 2016-May. p. 152-157 6 p. 7479192

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Authentication
Hardware
Hardware security
Networks (circuits)
Clocks

Message from the editor-in-chief

Togawa, N., 2016, In : IPSJ Transactions on System LSI Design Methodology. 9, p. 1 1 p.

Research output: Contribution to journalEditorial

Field programmable gate arrays (FPGA)
registers
platforms
Wave filters
Networks (circuits)
3 Citations (Scopus)

Partitioning-based multiplexer network synthesis for field-data extractors

Ito, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, International System on Chip Conference. IEEE Computer Society, Vol. 2016-February. p. 263-268 6 p. 7406960

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Engines

Pedestrian navigation based on landmark recognition using glass-type wearable devices

Yano, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800433

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
Navigation systems
navigation
Navigation
Glass

Redesign for untrusted gate-level netlists

Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 219-220 2 p. 7604706

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Pattern matching
Chemical activation

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 29, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-July. p. 978-981 4 p. 7527406

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Noise abatement
Electric power utilization
Measurement errors
Cryptography
Energy utilization
2 Citations (Scopus)

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Light emitting diodes
Microprocessor chips
Synchronization
Electric power utilization
2015
5 Citations (Scopus)

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error-correcting Codes
Reduction Method
Data storage equipment
Cell
Energy
1 Citation (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 244-247 4 p. 7032765

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Delay circuits
Costs
Scheduling
High level synthesis
2 Citations (Scopus)

A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kawamura, K., Hagio, Y., Shi, Y. & Togawa, N., 2015 Sep 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 122-125 4 p. 7285065

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Silicon
High level synthesis
2 Citations (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
1 Citation (Scopus)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Terada, K., Yanagisawa, M. & Togawa, N., 2015 Jul 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July. p. 2129-2132 4 p. 7169100

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
High level synthesis
1 Citation (Scopus)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Teradat, K., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 248-251 4 p. 7032766

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
High level synthesis
5 Citations (Scopus)

A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

Research output: Contribution to journalArticle

Scoring
Hardware
Benchmark
Classify
Outsourcing
1 Citation (Scopus)
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
1 Citation (Scopus)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 300-303 4 p. 7032779

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Monitoring
Networks (circuits)
Timing circuits
Error correction
3 Citations (Scopus)
Prediction Error
Insertion
Timing
Networks (circuits)
Checkpoint
1 Citation (Scopus)
High-level Synthesis
Energy Efficient
Clocks
Interconnect
Energy Saving