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Research Output 1994 2020

2015
43 Citations (Scopus)

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Apr 22, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-April. p. 465-470 6 p. 7092434

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Semiconductor materials
3 Citations (Scopus)

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 304-307 4 p. 7032780

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Hamming distance
Crosstalk
Radiation
Code generation
2 Citations (Scopus)
Hamming distance
Code Generation
Hamming Distance
Minimum Distance
Limiting
2 Citations (Scopus)
Code Generation
Data storage equipment
Error-correcting Codes
Energy
Static random access storage

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, Vol. 9427. 94270K

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Photoresists
Lithography
Clustering algorithms
Clustering Algorithm
Photoresist

In-situ timing monitoring methods for variation-resilient designs

Shi, Y. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 735-738 4 p. 7032886

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Monitoring
LSI circuits
Electric potential
Pipelines
Temperature
1 Citation (Scopus)

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Sep 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Information use
Side channel attack
3 Citations (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 252-255 4 p. 7032767

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Hardware
Side channel attack
1 Citation (Scopus)

Scan-based side-channel attack on the camellia block cipher using scan signatures

Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

Research output: Contribution to journalArticle

Side Channel Attacks
Block Cipher
Signature
Cryptography
Chip
4 Citations (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 555-558 4 p. 7032842

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Discrete Fourier transforms
Networks (circuits)
2014
5 Citations (Scopus)
Scheduling
High level synthesis
Silicon

Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

Akasaka, H., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2014, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 74-80 7 p.

Research output: Contribution to journalArticle

Clocks
Energy utilization
High level synthesis

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 others, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

Research output: Contribution to journalArticle

7 Citations (Scopus)

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Shio, M., Yanagisawa, M. & Togawa, N., 2014, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 1436-1439 4 p. 6865415

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Interpolation
Networks (circuits)
Adders
5 Citations (Scopus)
Stream Cipher
Shift registers
Signature
Attack
Internal
3 Citations (Scopus)

Scan-based attack on the LED block cipher using scan signatures

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 1460-1463 4 p. 6865421

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Computer hardware
3 Citations (Scopus)
Side Channel Attacks
Block Cipher
Encryption
Cryptography
Signature

Throughput driven check point selection in suspicious timing error prediction based designs

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 6820280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Throughput
Networks (circuits)
2013
Cache
Data structures
Simulator
High Speed
Simulators

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric potential
Energy conservation
Scheduling
High level synthesis

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kawamura, K., Tanaka, S., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1736-1739 4 p. 6572200

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
High level synthesis
1 Citation (Scopus)
High-level Synthesis
Chip
Interconnect
Energy Consumption
Energy utilization
1 Citation (Scopus)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1432-1435 4 p. 6572125

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
Side channel attack
Monitoring
1 Citation (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811826

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Energy utilization
Data storage equipment
Memory architecture
2 Citations (Scopus)
High-level Synthesis
Voltage
Electric potential
Floorplanning
Energy Saving
2 Citations (Scopus)

High-level synthesis with post-silicon delay tuning for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2013, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 194-197 4 p. 6863970

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tuning
Scheduling
Silicon
High level synthesis
2 Citations (Scopus)

Scan-based attack against DES and Triple DES cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2013, In : Journal of Information Processing. 21, 3, p. 572-579 8 p.

Research output: Contribution to journalArticle

Cryptography
2 Citations (Scopus)

Scan-based attack against Trivium stream cipher independent of scan structure

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811855

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shift registers
Side channel attack
14 Citations (Scopus)

Secure scan design with dynamically configurable connection

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2013, Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC. IEEE Computer Society, p. 256-262 7 p. 6820873

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Testing
14 Citations (Scopus)

Suspicious timing error prediction with in-cycle clock gating

Shi, Y., Igarashi, H., Togawa, N. & Yanagisawa, M., 2013, Proceedings - International Symposium on Quality Electronic Design, ISQED. p. 335-340 6 p. 6523631

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
Error detection
Energy efficiency
Electric power utilization
2012
Adders
Optical resolving power
Image resolution
Costs
Time delay
3 Citations (Scopus)

A hybrid NoC architecture utilizing packet transmission priority control method

Lee, S., Togawa, N., Sekihara, Y., Aoki, T. & Onozawa, A., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 404-407 4 p. 6419057

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Network-on-chip
Routers
Scalability
Servers
System-on-chip
1 Citation (Scopus)
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications
8 Citations (Scopus)

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. p. 576-579 4 p. 6272096

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy conservation
Electric potential
Scheduling
Controllers
High level synthesis

A novel BMNoC configuration algorithm utilizing communication volume and locality among cores

Lee, S., Togawa, N., Aoki, T. & Onozawa, A., 2012, ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. p. 1668-1671 4 p. 6271578

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Communication
Scalability
System-on-chip
Network-on-chip
24 Citations (Scopus)

Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 155-158 4 p. 6407063

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Design for testability
Side channel attack
13 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 106-117 12 p.

Research output: Contribution to journalArticle

Energy conservation
Electric potential
Semiconductor devices
Energy efficiency
Scheduling
2 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Energy utilization
High level synthesis
Electric potential
14 Citations (Scopus)
Networks (circuits)
synthesis
clocks
iteration
High level synthesis
19 Citations (Scopus)

Robust secure scan design against scan-based differential cryptanalysis

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 Jan, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

Research output: Contribution to journalArticle

13 Citations (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 599-602 4 p. 6419106

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Side channel attack
Countermeasures
Side Channel Attacks
Attack
Hardware Implementation
Hardware
6 Citations (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 607-610 4 p. 6419108

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Design for testability
Networks (circuits)
Side channel attack
1 Citation (Scopus)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 603-606 4 p. 6419107

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Field programmable gate arrays (FPGA)
Networks (circuits)
Costs
2011
1 Citation (Scopus)

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
12 Citations (Scopus)

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journalArticle

Scheduling
Error detection
High level synthesis
Embedded systems
Simulators
Hardware
Costs
4 Citations (Scopus)

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Simulators
Hardware
Costs
Experiments
Capacitance
Greedy Algorithm
Decoupling
Chip
Voltage
3 Citations (Scopus)
Network Design
Greedy Algorithm
Optimization Algorithm
Voltage
Electric wiring