If you made any changes in Pure these will be visible here soon.

Research Output 1994 2020

2011
6 Citations (Scopus)

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

Research output: Contribution to journalArticle

Cryptography
Networks (circuits)
Public key cryptography
Monitoring
Testing
3 Citations (Scopus)

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011, In : IEICE Electronics Express. 8, 14, p. 1161-1167 7 p.

Research output: Contribution to journalArticle

configurations
Embedded systems
simulation
Simulators
central processing units
2010

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1083-1086 4 p. 5774956

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fast Fourier transforms
3 Citations (Scopus)

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Lee, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 712-715 4 p. 5774825

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Scalability
Communication
Network-on-chip

Improved launch for higher TDF coverage with fewer test patterns

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

Research output: Contribution to journalArticle

Networks (circuits)
4 Citations (Scopus)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllers
Scheduling
High level synthesis
45 Citations (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 407-412 6 p. 5419848

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Networks (circuits)
Public key cryptography
Monitoring
46 Citations (Scopus)

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

Research output: Contribution to journalArticle

RSA Cryptosystem
Side Channel Attacks
Cryptography
Signature
Networks (circuits)
8 Citations (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Statistical methods
Hardware
Networks (circuits)
Side channel attack
1 Citation (Scopus)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Shi, Y., Tokumitsu, K., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1139-1142 4 p. 5774925

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
High definition television
Particle accelerators
Electric power utilization
Pixels
2009
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
29 Citations (Scopus)

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journalArticle

Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journalArticle

Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization
7 Citations (Scopus)

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec 15, Proceedings - International Test Conference. 5355900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Flip
Design
25 Citations (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 817-822 6 p. 4796581

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Data storage equipment
8 Citations (Scopus)
High-level Synthesis
Controllers
Floorplanning
Networks (circuits)
Controller

Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Sep, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

Research output: Contribution to journalArticle

Montgomery multiplication
Cryptography
Multiplier
Clocks
Time delay
Compaction
Masking
Unknown
Error detection
Masks
2008
3 Citations (Scopus)

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journalArticle

Cryptography
Failure analysis
Testing
Masking
Cost reduction
Masks
Compression
Unknown
1 Citation (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 705-708 4 p. 4746121

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Decoding
Throughput
HIgh speed networks
Mobile devices
4 Citations (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 701-704 4 p. 4746120

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FIR filters
Engines
Digital storage
Specifications
Processing
8 Citations (Scopus)

Floorplan-driven high-level synthesis for distributed/shared-register architectures

Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug, In : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

Research output: Contribution to journalArticle

Scheduling
Networks (circuits)
High level synthesis
5 Citations (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data compression
Networks (circuits)
Cost reduction
Product design
Masks
9 Citations (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Networks (circuits)
High level synthesis
LDPC Codes
Dissipation
Energy dissipation
Compression
Clocks
4 Citations (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Clocks
Time delay
Public key cryptography
Parallel architectures

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1779-1781 3 p. 4746386

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Masks
Degradation
2007
3 Citations (Scopus)

Design for secure test - A case study on pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2007, Proceedings - IEEE International Symposium on Circuits and Systems. p. 149-152 4 p. 4252593

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Hardware
Testing
Security of data
Data communication systems
3 Citations (Scopus)

Power-efficient LDPC code decoder architecture

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2007, Proceedings of the International Symposium on Low Power Electronics and Design. p. 359-362 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Energy dissipation
Throughput
Shift registers
Clocks
2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle

Cryptography
Hardware
1 Citation (Scopus)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 594-599 6 p. 1594750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Networks (circuits)
Communication
Specifications
System-on-chip
7 Citations (Scopus)

A parallel LSI architecture for LDPC decoder improving message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006, Proceedings - IEEE International Symposium on Circuits and Systems. p. 5099-5102 4 p. 1693779

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Hardware
Iterative decoding
Decoding
Throughput
14 Citations (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 653-658 6 p. 1594760

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cost reduction
Fans
Data compression
Product design
Costs

Memory-efficient accelerating schedule for LDPC decoder

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2006, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1317-1320 4 p. 4145643

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Data storage equipment
9 Citations (Scopus)

Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Apr, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

Research output: Contribution to journalArticle

Message passing
Message Passing
High Efficiency
Iterative decoding
Schedule
5 Citations (Scopus)

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

Research output: Contribution to journalArticle

Message passing
Message Passing
Schedule
Static random access storage
Energy dissipation
2 Citations (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. & 10 others, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.

Research output: Contribution to journalArticle

VLSI Design
Computer aided design
2005

A processor core synthesis system in IP-based SoC design

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. p. 286-291 6 p. 1466175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
System-on-chip
1 Citation (Scopus)

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journalArticle

Decomposition
17 Citations (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. Vol. 2005. p. 386-389 4 p. 1575460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Discrete Fourier transforms
Hardware
25 Citations (Scopus)

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005. p. 503-510 8 p. 1524200

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Decoding
Field programmable gate arrays (FPGA)
Pipelines
Hardware
3 Citations (Scopus)

Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

Research output: Contribution to journalArticle

Reed-Solomon codes
Adaptive systems
Error correction
Hardware
Communication channels (information theory)

Reconfigurable adaptive FEC system with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2. p. 1252-1255 4 p. 1466570

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive systems
Hardware
Error correction
Throughput

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

Research output: Contribution to journalArticle

Parallelism
Synthesis
Unit
Optimization
Timing

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings - IEEE International Symposium on Circuits and Systems. p. 3499-3502 4 p. 1465383

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Application programs
Data storage equipment
Hardware
Hardware
Software
Unit
Application programs
Cycle
2 Citations (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asian Test Symposium. p. 432-437 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coloring
Heuristic algorithms
Electric power utilization
System-on-chip