• 939 Citations
  • 15 h-Index
1994 …2020

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

2012

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058. (ISOCC 2012 - 2012 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
14 Citations (Scopus)

Robust secure scan design against scan-based differential cryptanalysis

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

Research output: Contribution to journalArticle

19 Citations (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 599-602 4 p. 6419106. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 607-610 4 p. 6419108. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 603-606 4 p. 6419107. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2011

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journalArticle

12 Citations (Scopus)

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
3 Citations (Scopus)

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011 Aug 1, In : ieice electronics express. 8, 14, p. 1161-1167 7 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)
2010

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 1083-1086 4 p. 5774956. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Lee, S. J., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 712-715 4 p. 5774825. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Improved launch for higher TDF coverage with fewer test patterns

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

Research output: Contribution to journalArticle

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 407-412 6 p. 5419848. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Citations (Scopus)

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

Research output: Contribution to journalArticle

48 Citations (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Shi, Y., Tokumitsu, K., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Dec 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 1139-1142 4 p. 5774925. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2009

An l1 cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.

Research output: Contribution to journalArticle

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journalArticle

32 Citations (Scopus)

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journalArticle

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec 15, International Test Conference, ITC 2009 - Proceedings. 5355900. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Apr 20, Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. p. 817-822 6 p. 4796581. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)
8 Citations (Scopus)

Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Sep, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

Research output: Contribution to journalArticle

2008

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Dec 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 705-708 4 p. 4746121. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008 Dec 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 701-704 4 p. 4746120. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Floorplan-driven high-level synthesis for distributed/shared-register architectures

Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug 1, In : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Sep 5, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Dec 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 1779-1781 3 p. 4746386. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2007

Design for secure test - A case study on pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2007 Sep 27, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 149-152 4 p., 4252593.

Research output: Contribution to journalConference article

3 Citations (Scopus)

Power-efficient LDPC code decoder architecture

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2007 Dec 17, ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. p. 359-362 4 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006 Jan 1, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 594-599 6 p. 1594750. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A parallel LSI architecture for LDPC decoder improving message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec 1, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 5099-5102 4 p. 1693779. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 Sep 19, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 653-658 6 p. 1594760. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Memory-efficient accelerating schedule for LDPC decoder

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec 1, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. p. 1317-1320 4 p. 4145643. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Apr, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)