• 939 Citations
  • 15 h-Index
1994 …2020

Research output per year

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Research Output

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1996 Dec 1, p. 294-297. 4 p.

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Personalized landmark recommendation algorithm based on language-specific satisfaction prediction using heterogeneous open data sources

Bao, S., Yanagisawa, M. & Togawa, N., 2018 Aug, Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018. Akbar Hussain, D. M., Tomar, G. S. & Tomar, G. S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 70-76 7 p. 8864958. (Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Personalized Landmark Recommendation for Language-Specific Users by Open Data Mining

Bao, S., Yanagisawa, M. & Togawa, N., 2019 Jan 1, Studies in Computational Intelligence. Springer-Verlag, p. 107-121 15 p. (Studies in Computational Intelligence; vol. 791).

Research output: Chapter in Book/Report/Conference proceedingChapter

1 Citation (Scopus)

Personalized one-day travel with multi-nearby-landmark recommendation

Bao, S., Yanagisawa, M. & Togawa, N., 2017 Dec 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, Vol. 2017-September. p. 239-242 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Power-efficient LDPC code decoder architecture

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2007 Dec 17, ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. p. 359-362 4 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)

Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Reconfigurable adaptive FEC system with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 Dec 1, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. p. 1252-1255 4 p. 1466570. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Redesign for untrusted gate-level netlists

Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 219-220 2 p. 7604706

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec 1, In : Midwest Symposium on Circuits and Systems. 2, p. II445-II448

Research output: Contribution to journalConference article

1 Citation (Scopus)

Road-illuminance level inference across road networks based on Bayesian analysis

Bao, S., Yanagisawa, M. & Togawa, N., 2018 Mar 26, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Robust AES circuit design for delay variation using suspicious timing error prediction

Yahagi, Y., Yanagisawa, M. & Togawa, N., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 101-102 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Robust indoor/outdoor detection method based on sparse GPS positioning information

Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, Vol. 2018-September. 8576188

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Robust secure scan design against scan-based differential cryptanalysis

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

Research output: Contribution to journalArticle

19 Citations (Scopus)

Rotator-based multiplexer network synthesis for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 2, Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. Bhatia, K., Alioto, M., Zhao, D., Marshall, A. & Sridhar, R. (eds.). IEEE Computer Society, p. 194-199 6 p. 7905464. (International System on Chip Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 29, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-July. p. 978-981 4 p. 7527406

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access
1 Citation (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Scan-based attack against DES and Triple DES cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2013 Jul 19, In : Journal of information processing. 21, 3, p. 572-579 8 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 599-602 4 p. 6419106. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 407-412 6 p. 5419848. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Citations (Scopus)

Scan-based attack against Trivium stream cipher independent of scan structure

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811855. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
5 Citations (Scopus)

Scan-based attack on the LED block cipher using scan signatures

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 Jan 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1460-1463 4 p. 6865421. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

Research output: Contribution to journalArticle

48 Citations (Scopus)

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Sep 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 252-255 4 p. 7032767. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Scan-based side-channel attack on the camellia block cipher using scan signatures

Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
3 Citations (Scopus)

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 555-558 4 p. 7032842. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Secure scan design with dynamically configurable connection

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 Jan 1, Proceedings - 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, PRDC 2013. IEEE Computer Society, p. 256-262 7 p. 6820873. (Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)
2 Citations (Scopus)

Simultaneous placement and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994 Dec 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 483-486 4 p.

Research output: Contribution to journalConference article

1 Citation (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, p. 125-128 4 p. (IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1997 Jan 1, p. 569-578. 10 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Simultaneous placement and global routing for transport-processing FPGA layout

Togawa, N., Sato, M. & Ohtsuki, T., 1996 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Soft error tolerant latch designs with low power consumption (invited paper)

Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 52-55 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. & 10 others, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, 1 p.

Research output: Contribution to journalEditorial

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011 Aug 1, In : ieice electronics express. 8, 14, p. 1161-1167 7 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 607-610 4 p. 6419108. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs

Ye, J., Togawa, N., Yanagisawa, M. & Shi, Y., 2019 Jan 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702386. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
5 Citations (Scopus)

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

Research output: Contribution to journalArticle

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Dec 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 3499-3502 4 p., 1465383.

Research output: Contribution to journalConference article