• 939 Citations
  • 15 h-Index
1994 …2020

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2016

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A landmark-based route recommendation method for pedestrian walking strategies

Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A low-power soft error tolerant latch scheme

Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. Buchner, T., Zhao, D., Bhatia, K. & Sridhar, R. (eds.). IEEE Computer Society, p. 7-12 6 p. 7406898. (International System on Chip Conference; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark

Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A visible corner-landmark based route finding algorithm for pedestrian navigation

Takeda, K., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 Feb 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 601-602 2 p. 7398498

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Jan 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Effective parallel algorithm for GPGPU-accelerated explicit routing optimization

Kikuta, K., Oki, E., Yamanaka, N., Togawa, N. & Nakazato, H., 2016 Feb 23, 2015 IEEE Global Communications Conference, GLOBECOM 2015. Institute of Electrical and Electronics Engineers Inc., 7416979

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Hardware Trojans classification for gate-level netlists based on machine learning

Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Hash-Table and balanced-Tree based fib architecture for ccn routers

Shimazaki, K., Aoki, T., Hatano, T., Otsuka, T., Miyazaki, A., Tsuda, T. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 67-68 2 p. 7799736

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

In-situ Trojan authentication for invalidating hardware-Trojan functions

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, Vol. 2016-May. p. 152-157 6 p. 7479192

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Partitioning-based multiplexer network synthesis for field-data extractors

Ito, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. Buchner, T., Zhao, D., Bhatia, K. & Sridhar, R. (eds.). IEEE Computer Society, p. 263-268 6 p. 7406960. (International System on Chip Conference; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Pedestrian navigation based on landmark recognition using glass-type wearable devices

Yano, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800433

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Redesign for untrusted gate-level netlists

Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 219-220 2 p. 7604706

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rotator-based multiplexer network synthesis for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 2, Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. Bhatia, K., Alioto, M., Zhao, D., Marshall, A. & Sridhar, R. (eds.). IEEE Computer Society, p. 194-199 6 p. 7905464. (International System on Chip Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 29, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-July. p. 978-981 4 p. 7527406

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2015

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 244-247 4 p. 7032765. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kawamura, K., Hagio, Y., Shi, Y. & Togawa, N., 2015 Sep 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 122-125 4 p. 7285065

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Terada, K., Yanagisawa, M. & Togawa, N., 2015 Jul 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July. p. 2129-2132 4 p. 7169100

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Teradat, K., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 248-251 4 p. 7032766. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 300-303 4 p. 7032779. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Apr 22, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-April. p. 465-470 6 p. 7092434

Research output: Chapter in Book/Report/Conference proceedingConference contribution

50 Citations (Scopus)

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 304-307 4 p. 7032780. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, Vol. 9427. 94270K

Research output: Chapter in Book/Report/Conference proceedingConference contribution

In-situ timing monitoring methods for variation-resilient designs

Shi, Y. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 735-738 4 p. 7032886. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Sep 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 252-255 4 p. 7032767. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 555-558 4 p. 7032842. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
2014

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Shio, M., Yanagisawa, M. & Togawa, N., 2014 Jan 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1436-1439 4 p. 6865415. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Scan-based attack on the LED block cipher using scan signatures

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 Jan 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1460-1463 4 p. 6865421. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Throughput driven check point selection in suspicious timing error prediction based designs

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2014 Jan 1, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 6820280. (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2013

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 Aug 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kawamura, K., Tanaka, S., Yanagisawa, M. & Togawa, N., 2013 Sep 9, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 1736-1739 4 p. 6572200. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 Sep 9, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 1432-1435 4 p. 6572125. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811826. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

High-level synthesis with post-silicon delay tuning for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2013 Jan 1, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 194-197 4 p. 6863970. (ISOCC 2013 - 2013 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Scan-based attack against Trivium stream cipher independent of scan structure

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811855. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Secure scan design with dynamically configurable connection

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 Jan 1, Proceedings - 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, PRDC 2013. IEEE Computer Society, p. 256-262 7 p. 6820873. (Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Suspicious timing error prediction with in-cycle clock gating

Shi, Y., Igarashi, H., Togawa, N. & Yanagisawa, M., 2013 Jul 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 335-340 6 p. 6523631. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)
2012

A hybrid NoC architecture utilizing packet transmission priority control method

Lee, S., Togawa, N., Sekihara, Y., Aoki, T. & Onozawa, A., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 404-407 4 p. 6419057. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 Dec 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 155-158 4 p. 6407063. (ISOCC 2012 - 2012 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058. (ISOCC 2012 - 2012 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 599-602 4 p. 6419106. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 Dec 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 607-610 4 p. 6419108. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)