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Research Output 1994 2020

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Conference contribution
Conference contribution

Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection

Nishizawa, M., Hasegawa, K. & Togawa, N., 2019 Jan 8, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 362-365 4 p. 8605668. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Capacitance measurement
hardware
Capacitance
capacitance
Hardware
3 Citations (Scopus)

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Clocks
High level synthesis
Networks (circuits)
2 Citations (Scopus)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
routes
wrist
Information services
partitions
1 Citation (Scopus)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1432-1435 4 p. 6572125

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
Side channel attack
Monitoring
3 Citations (Scopus)

Design for secure test - A case study on pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2007, Proceedings - IEEE International Symposium on Circuits and Systems. p. 149-152 4 p. 4252593

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Hardware
Testing
Security of data
Data communication systems
7 Citations (Scopus)

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec 15, Proceedings - International Test Conference. 5355900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Flip
Design
6 Citations (Scopus)

Designing hardware trojans and their detection based on a SVM-based approach

Inoue, T., Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 811-814 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Support vector machines
Hardware
Learning systems
Classifiers
Transceivers

Designing subspecies of hardware trojans and their detection using neural network approach

Inoue, T., Hasegawa, K., Kobayashi, Y., Yanagisawa, M. & Togawa, N., 2018 Dec 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, Vol. 2018-September. 8576247

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neural networks
Hardware
Trigger circuits
Domestic appliances
Learning systems
1 Citation (Scopus)

Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 Sep 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 97-102 6 p. 8474113

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Microcontrollers
Television
Electric power utilization
Hardware
Internet of things
25 Citations (Scopus)

Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 155-158 4 p. 6407063

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Design for testability
Side channel attack
1 Citation (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 705-708 4 p. 4746121

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Decoding
Throughput
HIgh speed networks
Mobile devices
1 Citation (Scopus)

Effective parallel algorithm for GPGPU-accelerated explicit routing optimization

Kikuta, K., Oki, E., Yamanaka, N., Togawa, N. & Nakazato, H., 2016 Feb 23, 2015 IEEE Global Communications Conference, GLOBECOM 2015. Institute of Electrical and Electronics Engineers Inc., 7416979

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer programming
Parallel algorithms
programming
Program processors
Genetic algorithms

Effective write-reduction method for MLC non-volatile memory

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Durability
Embedded systems

Efficient Ising Model Mapping to Solving Slot Placement Problem

Kanamaru, S., Oku, D., Tawada, M., Tanaka, S., Hayashi, M., Yamaoka, M., Yanagisawa, M. & Togawa, N., 2019 Mar 6, 2019 IEEE International Conference on Consumer Electronics, ICCE 2019. Institute of Electrical and Electronics Engineers Inc., 8661947. (2019 IEEE International Conference on Consumer Electronics, ICCE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ising model
Combinatorial optimization
Hamiltonians
Electric wiring
Simulated annealing

Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis

Hasegawa, K., Chikamatsu, K. & Togawa, N., 2019 Jul, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 54-57 4 p. 8854456. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllers
Costs
Hardware
Electric power utilization
Experiments
2 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Energy utilization
High level synthesis
Electric potential
1 Citation (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811826

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Energy utilization
Data storage equipment
Memory architecture

Error Correction Coding of Stochastic Numbers Using BER Measurement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2019 Jul, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 243-246 4 p. 8854450. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error correction
Bit error rate
Signal to noise ratio
Networks (circuits)
4 Citations (Scopus)

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Simulators
Hardware
Costs
Experiments
25 Citations (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 817-822 6 p. 4796581

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Data storage equipment

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 161-164 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electron energy levels
Clocks
Synchronization
Networks (circuits)
High level synthesis

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, Vol. 9427. 94270K

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Photoresists
Lithography
Clustering algorithms
Clustering Algorithm
Photoresist
14 Citations (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 653-658 6 p. 1594760

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cost reduction
Fans
Data compression
Product design
Costs
4 Citations (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 701-704 4 p. 4746120

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FIR filters
Engines
Digital storage
Specifications
Processing

Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

Asai, D., Yanagisawa, M. & Togawa, N., 2018 Jan 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, Vol. 2017-October. p. 64-67 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy harvesting
Networks (circuits)
High level synthesis
Energy utilization
Scheduling
5 Citations (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data compression
Networks (circuits)
Cost reduction
Product design
Masks
1 Citation (Scopus)

Hardware Trojan detection and classification based on steady state learning

Oya, M., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Networks (circuits)
Hardware security

Hardware Trojan Detection Utilizing Machine Learning Approaches

Hasegawa, K., Shi, Y. & Togawa, N., 2018 Sep 5, Proceedings - 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications and 12th IEEE International Conference on Big Data Science and Engineering, Trustcom/BigDataSE 2018. Institute of Electrical and Electronics Engineers Inc., p. 1891-1896 6 p. 8456155

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Learning systems
Hardware
Outsourcing
Hardware security
Machine learning
24 Citations (Scopus)

Hardware Trojans classification for gate-level netlists based on machine learning

Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 Oct 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Support vector machines
Learning systems
Hardware
Classifiers
Hardware security
21 Citations (Scopus)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Sep 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multilayer neural networks
Hardware
Outsourcing
Learning systems
Integrated circuit design
1 Citation (Scopus)

Hash-Table and balanced-Tree based fib architecture for ccn routers

Shimazaki, K., Aoki, T., Hatano, T., Otsuka, T., Miyazaki, A., Tsuda, T. & Togawa, N., 2016 Dec 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 67-68 2 p. 7799736

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Next generation networks
data structures
Data structures
Servers
9 Citations (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Networks (circuits)
High level synthesis
2 Citations (Scopus)

High-level synthesis with post-silicon delay tuning for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2013, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 194-197 4 p. 6863970

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tuning
Scheduling
Silicon
High level synthesis
2 Citations (Scopus)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
Pixels
Delay circuits
Data storage equipment

Implementation evaluation of scan-based attack against a Trivium cipher circuit

Oku, D., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 220-223 4 p. 7803938

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
Processing

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Monitoring
2 Citations (Scopus)

Indoor navigation based on real-Time direction information generation using wearable glasses

Iwanaji, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2017 Jan 3, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 7804754

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Navigation systems
navigation
Navigation
Glass
landmarks

In-situ timing monitoring methods for variation-resilient designs

Shi, Y. & Togawa, N., 2015 Feb 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-February. p. 735-738 4 p. 7032886

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Monitoring
LSI circuits
Electric potential
Pipelines
Temperature
4 Citations (Scopus)

In-situ Trojan authentication for invalidating hardware-Trojan functions

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, Vol. 2016-May. p. 152-157 6 p. 7479192

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Authentication
Hardware
Hardware security
Networks (circuits)
Clocks
3 Citations (Scopus)

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 743-750 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition

Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis

Bao, S., Yanagisawa, M. & Togawa, N., 2019 Jan 22, Proceedings - 2018 IEEE International Conference on Big Data, Big Data 2018. Song, Y., Liu, B., Lee, K., Abe, N., Pu, C., Qiao, M., Ahmed, N., Kossmann, D., Saltz, J., Tang, J., He, J., Liu, H. & Hu, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 3628-3637 10 p. 8622103. (Proceedings - 2018 IEEE International Conference on Big Data, Big Data 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Recommender systems
7 Citations (Scopus)

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Shio, M., Yanagisawa, M. & Togawa, N., 2014, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 1436-1439 4 p. 6865415

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Interpolation
Networks (circuits)
Adders
17 Citations (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. Vol. 2005. p. 386-389 4 p. 1575460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Discrete Fourier transforms
Hardware

Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 554-559 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1 Citation (Scopus)

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization

Togawa, N., Sato, M. & Ohtsuki, T., 1995, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, p. 319-327 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)

Memory-efficient accelerating schedule for LDPC decoder

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2006, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1317-1320 4 p. 4145643

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Data storage equipment
26 Citations (Scopus)

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005. p. 503-510 8 p. 1524200

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Decoding
Field programmable gate arrays (FPGA)
Pipelines
Hardware
3 Citations (Scopus)

Partitioning-based multiplexer network synthesis for field-data extractors

Ito, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Feb 12, International System on Chip Conference. IEEE Computer Society, Vol. 2016-February. p. 263-268 6 p. 7406960

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Engines

Pedestrian navigation based on landmark recognition using glass-type wearable devices

Yano, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 Dec 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800433

Research output: Chapter in Book/Report/Conference proceedingConference contribution

landmarks
Navigation systems
navigation
Navigation
Glass
4 Citations (Scopus)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllers
Scheduling
High level synthesis