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Research Output 1994 2020

Filter
Conference contribution
2008
1 Citation (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 705-708 4 p. 4746121

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Decoding
Throughput
HIgh speed networks
Mobile devices
4 Citations (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 701-704 4 p. 4746120

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FIR filters
Engines
Digital storage
Specifications
Processing
5 Citations (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data compression
Networks (circuits)
Cost reduction
Product design
Masks
9 Citations (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Networks (circuits)
High level synthesis
4 Citations (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Clocks
Time delay
Public key cryptography
Parallel architectures

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1779-1781 3 p. 4746386

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Masks
Degradation
2007
3 Citations (Scopus)

Design for secure test - A case study on pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2007, Proceedings - IEEE International Symposium on Circuits and Systems. p. 149-152 4 p. 4252593

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Hardware
Testing
Security of data
Data communication systems
3 Citations (Scopus)

Power-efficient LDPC code decoder architecture

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2007, Proceedings of the International Symposium on Low Power Electronics and Design. p. 359-362 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Energy dissipation
Throughput
Shift registers
Clocks
2006
1 Citation (Scopus)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 594-599 6 p. 1594750

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Networks (circuits)
Communication
Specifications
System-on-chip
7 Citations (Scopus)

A parallel LSI architecture for LDPC decoder improving message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006, Proceedings - IEEE International Symposium on Circuits and Systems. p. 5099-5102 4 p. 1693779

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Hardware
Iterative decoding
Decoding
Throughput
14 Citations (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 653-658 6 p. 1594760

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cost reduction
Fans
Data compression
Product design
Costs

Memory-efficient accelerating schedule for LDPC decoder

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2006, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1317-1320 4 p. 4145643

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Data storage equipment
2005

A processor core synthesis system in IP-based SoC design

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. p. 286-291 6 p. 1466175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
System-on-chip
17 Citations (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. Vol. 2005. p. 386-389 4 p. 1575460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Discrete Fourier transforms
Hardware
25 Citations (Scopus)

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005. p. 503-510 8 p. 1524200

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Message passing
Decoding
Field programmable gate arrays (FPGA)
Pipelines
Hardware

Reconfigurable adaptive FEC system with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2. p. 1252-1255 4 p. 1466570

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive systems
Hardware
Error correction
Throughput

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings - IEEE International Symposium on Circuits and Systems. p. 3499-3502 4 p. 1465383

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Application programs
Data storage equipment
Hardware
2 Citations (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asian Test Symposium. p. 432-437 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coloring
Heuristic algorithms
Electric power utilization
System-on-chip
1 Citation (Scopus)

An efficient algorithm/architecture codesign for image encoders

Choi, J., Togawa, N., Ikenaga, T., Goto, S., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Motion estimation
Computational complexity
Bandwidth
Data storage equipment
4 Citations (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 13-16 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive systems
Hardware
Communication
Error correction
Throughput
4 Citations (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 74-79 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Clocks
Synchronization
High level synthesis

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. p. 161-164 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electron energy levels
Clocks
Synchronization
Networks (circuits)
High level synthesis
3 Citations (Scopus)

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 743-750 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition
1 Citation (Scopus)

Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data compression
Glossaries
Synchronization
Costs
System-on-chip
2003
2 Citations (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2003-January. p. 135-140 6 p. 1195006

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Application programs
2002

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., Vol. 1. p. 171-176 6 p. 1114930

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
4 Citations (Scopus)

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Motion estimation
Computer hardware description languages
Reconfigurable architectures
Computer hardware
Electric power utilization
2001
6 Citations (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 156-161 6 p. 913297

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital signal processors
Hardware
Application programs
2000
1 Citation (Scopus)

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. p. 544-547 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital signal processors
Hardware
6 Citations (Scopus)

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 309-312 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Application programs
Flow control
Flow graphs
Computer hardware
1997
5 Citations (Scopus)

Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 569-578 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
Processing
Delay circuits
1996
2 Citations (Scopus)

Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1996, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 294-297 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
1995
1 Citation (Scopus)

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization

Togawa, N., Sato, M. & Ohtsuki, T., 1995, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, p. 319-327 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1994

Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 554-559 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1 Citation (Scopus)

Simultaneous placement and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994, Proceedings - IEEE International Symposium on Circuits and Systems. IEEE, Vol. 1. p. 483-486 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)