• 939 Citations
  • 15 h-Index
1994 …2020

Research output per year

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Research Output

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2012

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012 Sep 28, p. 576-579. 4 p.

Research output: Contribution to conferencePaper

8 Citations (Scopus)

A novel BMNoC configuration algorithm utilizing communication volume and locality among cores

Lee, S., Togawa, N., Aoki, T. & Onozawa, A., 2012 Sep 28, p. 1668-1671. 4 p.

Research output: Contribution to conferencePaper

2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 250-255. 6 p.

Research output: Contribution to conferencePaper

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004 Dec 1, p. 13-16. 4 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 74-79. 6 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec 1, p. 161-164. 4 p.

Research output: Contribution to conferencePaper

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004 Jun 1, p. 743-750. 8 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)
2000

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, p. 544-547. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)
1998

High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Togawa, N., Hisaki, T., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, p. 265-274. 10 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 Dec 1, p. 519-526. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)
1997

Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1997 Jan 1, p. 569-578. 10 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)
1996

Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1996 Dec 1, p. 294-297. 4 p.

Research output: Contribution to conferencePaper

2 Citations (Scopus)
1995

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization

Togawa, N., Sato, M. & Ohtsuki, T., 1995 Dec 1, p. 319-327. 9 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)
1994

Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994 Dec 1, p. 554-559. 6 p.

Research output: Contribution to conferencePaper