• 889 Citations
  • 14 h-Index
1994 …2020

Research output per year

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2019

A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019 Jan 1, In : IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

Research output: Contribution to journalArticle

Open Access

A multiple cyclic-route generation method with route length constraint considering point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

Research output: Contribution to journalArticle

An FPGA implementation method based on distributed-register architectures

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

Research output: Contribution to journalArticle

Open Access
1 Citation (Scopus)
2018
1 Citation (Scopus)
2 Citations (Scopus)
3 Citations (Scopus)
2017
11 Citations (Scopus)
1 Citation (Scopus)

Efficient multiplexer networks for field-data extractors and their evaluations

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)
2016
1 Citation (Scopus)

A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Bi-partitioning based multiplexer network for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)
2015

A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)
1 Citation (Scopus)
3 Citations (Scopus)
1 Citation (Scopus)
2 Citations (Scopus)
2 Citations (Scopus)

Scan-based side-channel attack on the camellia block cipher using scan signatures

Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2014
5 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

Akasaka, H., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2014, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 74-80 7 p.

Research output: Contribution to journalArticle

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 others, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)
3 Citations (Scopus)
2013
1 Citation (Scopus)
2 Citations (Scopus)

Scan-based attack against DES and Triple DES cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2013, In : Journal of Information Processing. 21, 3, p. 572-579 8 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2012
1 Citation (Scopus)

Energy-efficient high-level synthesis for HDR architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 106-117 12 p.

Research output: Contribution to journalArticle

13 Citations (Scopus)
14 Citations (Scopus)

Robust secure scan design against scan-based differential cryptanalysis

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 Jan, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

Research output: Contribution to journalArticle

19 Citations (Scopus)
2011

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journalArticle

12 Citations (Scopus)