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Research Output 1994 2019

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2019

A multiple cyclic-route generation method with route length constraint considering point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

Research output: Contribution to journalArticle

Reference Point
User Preferences
Search Methods

An FPGA implementation method based on distributed-register architectures

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

Research output: Contribution to journalArticle

Open Access
Field programmable gate arrays (FPGA)
Networks (circuits)
2018
Soft Error
Trigger
Power Consumption
Electric power utilization
Double Sampling
Error-correcting Codes
Data storage equipment
Systematic Error
Crosstalk
Error Correction
1 Citation (Scopus)
Location Estimation
Positioning
Global positioning system
Mobile devices
Mobile Devices
Multilayer Neural Network
Multilayer neural networks
Hardware
Optimization
Evaluation
Approximate Design
Adders
Gears
Formulation
Energy Consumption
Hardware
Logic
Testing
Transition State
Integrated Circuits
Networks (circuits)
Side channel attack
Processing
2 Citations (Scopus)
Rearrangement
Networks (circuits)
Logic circuits
Mean square error
Inaccurate
2017
High-level Synthesis
Controller
Controllers
Unit
Hardware Design
High-level Synthesis
Bias voltage
Leakage
Data flow graphs
Energy
7 Citations (Scopus)
Learning systems
Machine Learning
Hardware
Support vector machines
Neural networks
1 Citation (Scopus)
Landmarks
Lighting
Count
Safety
Algorithm Design
Extractor
Wire
Evaluation
Networks (circuits)
Partitioning
Random Forest
Feature Extraction
Learning systems
Feature extraction
Hardware
2016
1 Citation (Scopus)
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many

A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

Research output: Contribution to journalArticle

Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement
1 Citation (Scopus)
Extractor
Partitioning
Stream Processing
Consecutive
Count
6 Citations (Scopus)

Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

Research output: Contribution to journalArticle

Quantitative Evaluation
Pattern matching
Pattern Matching
Hardware
Benchmark
2015
2 Citations (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
5 Citations (Scopus)

A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

Research output: Contribution to journalArticle

Scoring
Hardware
Benchmark
Classify
Outsourcing
1 Citation (Scopus)
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
2 Citations (Scopus)
Prediction Error
Insertion
Timing
Networks (circuits)
Checkpoint
1 Citation (Scopus)
High-level Synthesis
Energy Efficient
Clocks
Interconnect
Energy Saving
2 Citations (Scopus)
Hamming distance
Code Generation
Hamming Distance
Minimum Distance
Limiting
2 Citations (Scopus)
Code Generation
Data storage equipment
Error-correcting Codes
Energy
Static random access storage
1 Citation (Scopus)

Scan-based side-channel attack on the camellia block cipher using scan signatures

Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

Research output: Contribution to journalArticle

Side Channel Attacks
Block Cipher
Signature
Cryptography
Chip
2014
5 Citations (Scopus)
Scheduling
High level synthesis
Silicon

Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

Akasaka, H., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2014, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 74-80 7 p.

Research output: Contribution to journalArticle

Clocks
Energy utilization
High level synthesis

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 othersTogawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)
Stream Cipher
Shift registers
Signature
Attack
Internal
3 Citations (Scopus)
Side Channel Attacks
Block Cipher
Encryption
Cryptography
Signature
2013
Cache
Data structures
Simulator
High Speed
Simulators
1 Citation (Scopus)
High-level Synthesis
Chip
Interconnect
Energy Consumption
Energy utilization
2 Citations (Scopus)
High-level Synthesis
Voltage
Electric potential
Floorplanning
Energy Saving
2 Citations (Scopus)

Scan-based attack against DES and Triple DES cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2013, In : Journal of Information Processing. 21, 3, p. 572-579 8 p.

Research output: Contribution to journalArticle

Cryptography
2012
Adders
Optical resolving power
Image resolution
Costs
Time delay
1 Citation (Scopus)
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications
13 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 106-117 12 p.

Research output: Contribution to journalArticle

Energy conservation
Electric potential
Semiconductor devices
Energy efficiency
Scheduling
14 Citations (Scopus)
Networks (circuits)
synthesis
clocks
iteration
High level synthesis
17 Citations (Scopus)

Robust secure scan design against scan-based differential cryptanalysis

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 Jan, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

Research output: Contribution to journalArticle

Countermeasures
Side Channel Attacks
Attack
Hardware Implementation
Hardware
2011
1 Citation (Scopus)

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
12 Citations (Scopus)

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journalArticle

Scheduling
Error detection
High level synthesis
Embedded systems
Simulators
Hardware
Costs
Capacitance
Greedy Algorithm
Decoupling
Chip
Voltage
3 Citations (Scopus)
Network Design
Greedy Algorithm
Optimization Algorithm
Voltage
Electric wiring
6 Citations (Scopus)

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

Research output: Contribution to journalArticle

Cryptography
Networks (circuits)
Public key cryptography
Monitoring
Testing
3 Citations (Scopus)

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011, In : IEICE Electronics Express. 8, 14, p. 1161-1167 7 p.

Research output: Contribution to journalArticle

configurations
Embedded systems
simulation
Simulators
central processing units