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Research Output 1994 2020

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Article
1994
12 Citations (Scopus)
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
Maple
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
1995
2 Citations (Scopus)

Circuit partitioning algorithm with replication capability for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1995 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Replication
Field programmable gate arrays (FPGA)
Partitioning
Chip
1996
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
Path
3 Citations (Scopus)

Simultaneous placement and global routing for transport-processing FPGA layout

Togawa, N., Sato, M. & Ohtsuki, T., 1996, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.

Research output: Contribution to journalArticle

Field Programmable Gate Array
Placement
Table lookup
Field programmable gate arrays (FPGA)
Layout
1997
3 Citations (Scopus)
Field Programmable Gate Array
Critical Path
Field programmable gate arrays (FPGA)
Partitioning
Path

A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1997 Oct, In : Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Networks (circuits)

Fast scheduling and allocation algorithms for entropy CODEC

Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

Research output: Contribution to journalArticle

Flow graphs
Entropy
Scheduling
Scheduling algorithms
Merging
1998
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
7 Citations (Scopus)
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1999
1 Citation (Scopus)
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
16 Citations (Scopus)
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journalArticle

Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
2000
9 Citations (Scopus)
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
1 Citation (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

Research output: Contribution to journalArticle

Associative storage
Synthesis
Application programs
Unit
Memory Function
2001
1 Citation (Scopus)
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors
4 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journalArticle

Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
2002
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
3 Citations (Scopus)
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages
4 Citations (Scopus)
Power System
Power Consumption
Clocks
Electric power utilization
High-level Synthesis
2003

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journalArticle

Associative storage
Software System
Hardware
Application programs
Memory Function
2 Citations (Scopus)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journalArticle

Hardware/software Partitioning
Hardware
Unit
Timing
Configuration

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journalArticle

Simulator
Simulators
Generator
Hardware
Application programs
2004
Hardware
Software
Unit
Application programs
Cycle
2 Citations (Scopus)

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

Research output: Contribution to journalArticle

Error correction
Error Correction
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Reconfigurable Systems

High-level power optimization based on thread partitioning

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

Research output: Contribution to journalArticle

Thread
Partitioning
Optimization
Networks (circuits)
High-level Synthesis
2005
1 Citation (Scopus)

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journalArticle

Decomposition
3 Citations (Scopus)

Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

Research output: Contribution to journalArticle

Reed-Solomon codes
Adaptive systems
Error correction
Hardware
Communication channels (information theory)

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

Research output: Contribution to journalArticle

Parallelism
Synthesis
Unit
Optimization
Timing
2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle

Cryptography
Hardware
9 Citations (Scopus)

Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Apr, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

Research output: Contribution to journalArticle

Message passing
Message Passing
High Efficiency
Iterative decoding
Schedule
5 Citations (Scopus)

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

Research output: Contribution to journalArticle

Message passing
Message Passing
Schedule
Static random access storage
Energy dissipation
2 Citations (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. & 10 others, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.

Research output: Contribution to journalArticle

VLSI Design
Computer aided design
2008
3 Citations (Scopus)

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journalArticle

Cryptography
Failure analysis
Testing
Masking
Cost reduction
Masks
Compression
Unknown
8 Citations (Scopus)

Floorplan-driven high-level synthesis for distributed/shared-register architectures

Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug, In : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

Research output: Contribution to journalArticle

Scheduling
Networks (circuits)
High level synthesis
LDPC Codes
Dissipation
Energy dissipation
Compression
Clocks
2009
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
29 Citations (Scopus)

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journalArticle

Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journalArticle

Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization
8 Citations (Scopus)
High-level Synthesis
Controllers
Floorplanning
Networks (circuits)
Controller

Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Sep, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

Research output: Contribution to journalArticle

Montgomery multiplication
Cryptography
Multiplier
Clocks
Time delay
Compaction
Masking
Unknown
Error detection
Masks
2010

Improved launch for higher TDF coverage with fewer test patterns

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

Research output: Contribution to journalArticle

Networks (circuits)
46 Citations (Scopus)

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

Research output: Contribution to journalArticle

RSA Cryptosystem
Side Channel Attacks
Cryptography
Signature
Networks (circuits)
2011
1 Citation (Scopus)

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

Fast Fourier transforms