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Research Output 1994 2020

Filter
Article
High-level Synthesis
Controller
Controllers
Unit
Hardware Design
1 Citation (Scopus)
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many
3 Citations (Scopus)
Field Programmable Gate Array
Critical Path
Field programmable gate arrays (FPGA)
Partitioning
Path
5 Citations (Scopus)
Scheduling
High level synthesis
Silicon
1 Citation (Scopus)
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journalArticle

Cryptography
Hardware
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
1 Citation (Scopus)

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journalArticle

Fast Fourier transforms
Adders
Optical resolving power
Image resolution
Costs
Time delay
12 Citations (Scopus)

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journalArticle

Scheduling
Error detection
High level synthesis
High-level Synthesis
Bias voltage
Leakage
Data flow graphs
Energy
2 Citations (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs

A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019 Jan 1, In : IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

Research output: Contribution to journalArticle

Open Access
Ising model
Combinatorial optimization
Annealing
Chain length
Ground state
Hardware
Software
Unit
Application programs
Cycle
16 Citations (Scopus)
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware
9 Citations (Scopus)
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journalArticle

Associative storage
Software System
Hardware
Application programs
Memory Function
2 Citations (Scopus)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journalArticle

Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
9 Citations (Scopus)
Learning systems
Machine Learning
Hardware
Support vector machines
Neural networks
5 Citations (Scopus)

A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

Research output: Contribution to journalArticle

Scoring
Hardware
Benchmark
Classify
Outsourcing
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
1 Citation (Scopus)
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow

A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

Research output: Contribution to journalArticle

Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement
Cache
Data structures
Simulator
High Speed
Simulators
1 Citation (Scopus)
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications
Soft Error
Trigger
Power Consumption
Electric power utilization
Double Sampling

A multiple cyclic-route generation method with route length constraint considering point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

Research output: Contribution to journalArticle

Reference Point
User Preferences
Search Methods
3 Citations (Scopus)
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages
1 Citation (Scopus)
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
3 Citations (Scopus)
Prediction Error
Insertion
Timing
Networks (circuits)
Checkpoint
1 Citation (Scopus)
High-level Synthesis
Energy Efficient
Clocks
Interconnect
Energy Saving
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors

An FPGA implementation method based on distributed-register architectures

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

Research output: Contribution to journalArticle

Open Access
Field programmable gate arrays (FPGA)
Networks (circuits)
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration

A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1997 Oct, In : Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Networks (circuits)
4 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journalArticle

Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
Error-correcting Codes
Data storage equipment
Systematic Error
Crosstalk
Error Correction

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journalArticle

Simulator
Simulators
Generator
Hardware
Application programs
1 Citation (Scopus)
Global positioning system
Classifiers
Random Forest
Learning systems
Classify
1 Citation (Scopus)
Landmarks
Lighting
Count
Safety
Algorithm Design
29 Citations (Scopus)

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journalArticle

Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)
3 Citations (Scopus)

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journalArticle

Cryptography
Failure analysis
Testing
1 Citation (Scopus)

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journalArticle

Decomposition

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journalArticle

Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
Path
2 Citations (Scopus)
Location Estimation
Positioning
Global positioning system
Mobile devices
Mobile Devices
1 Citation (Scopus)
High-level Synthesis
Chip
Interconnect
Energy Consumption
Energy utilization

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journalArticle

Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization