Nozomu Togawa

Research output

Research output per year 1994 2012 2015 2016 2017 2018 2019 2020 2021 2022

• 150 Conference contribution
• 115 Article
• 14 Paper
• 6 Conference article
• 9 More
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

Research output per year

Research output per year

Search results

• Article

  A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 48%
  • Controllers 27%

• A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Code Generation 100%
  • Error-correcting Codes 67%
  • Clustering 54%
  • Data storage equipment 34%
  • Crosstalk 15%
  1 Citation (Scopus)

• A capacitance measurement device for running hardware devices and its evaluations

  Nishizawa, M., Hasegawa, K. & Togawa, N., 2020 Sep 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E103A, 9, p. 1018-1027 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Capacitance measurement 100%
  • Capacitance 92%
  • Hardware 84%
  • Evaluation 50%
  • Computer hardware 40%

• A circuit partitioning algorithm with path delay constraints for multi-FPGA systems

  Togawa, N., 1997 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Field Programmable Gate Array 100%
  • Critical Path 75%
  • Partitioning 63%
  • Field programmable gate arrays (FPGA) 51%
  • Chip 50%
  3 Citations (Scopus)

• A delay-variation-aware high-level synthesis algorithm for RDR architectures

  Hagio, Y., Yanagisawa, M. & Togawa, N., 2014, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 81-90 10 p.

  Research output: Contribution to journal › Article › peer-review

  • High level synthesis 100%
  • Scheduling 53%
  • Silicon 10%
  5 Citations (Scopus)

• A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

  Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Logic 100%
  • Boolean Networks 60%
  • Minimise 33%
  • Look-up Table 30%
  • Table lookup 25%
  1 Citation (Scopus)

• A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

  Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In: IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Cryptography 100%
  • Time 43%
  • Computer hardware 11%

• A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Scheduling Algorithm 100%
  • Fast Algorithm 68%
  • Scheduling algorithms 67%
  • Synthesis 61%
  • Connectivity 46%

• A fast selector-based subtract-multiplication unit and its application to butterfly unit

  Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Fast Fourier transforms 100%
  1 Citation (Scopus)

• A fastweighted adder by reducing partial product for reconstruction in super-resolution

  Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Adders 100%
  • Optical resolving power 24%
  • Image resolution 19%
  • Time delay 15%
  • Costs 13%

• A fault-secure high-level synthesis algorithm for RDR architectures

  Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

  Research output: Contribution to journal › Article › peer-review

  • High level synthesis 100%
  • Scheduling 26%
  • Error detection 21%
  12 Citations (Scopus)

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • Leakage 66%
  • High level synthesis 64%
  • Bias voltage 63%
  • Compensation and Redress 38%

• A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

  Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • Field Programmable Gate Array 79%
  • High level synthesis 64%
  • Field programmable gate arrays (FPGA) 41%
  • Design 31%
  2 Citations (Scopus)

• A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

  Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019, In: IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Ising model 100%
  • Annealing 62%
  • Combinatorial optimization 46%
  • Ground state 15%
  • Chain length 14%
  7 Citations (Scopus)

• A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

  Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Apr, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware 100%
  • Software 73%
  • Banks 50%
  • Computer hardware 48%
  • Unit 42%

• A hard ware/S oft ware cosynthesis system for digital signal processor cores

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.

  Research output: Contribution to journal › Article › peer-review

  • Digital Signal Processor 100%
  • Digital signal processors 57%
  • Application programs 47%
  • Hardware 42%
  • kernel 35%
  17 Citations (Scopus)

• A hardware/software cosynthesis system for digital signal processor cores with two types of register files

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Digital Signal Processor 100%
  • Software System 72%
  • Hardware 63%
  • Digital signal processors 57%
  • Digital Signal Processing 37%
  9 Citations (Scopus)

• A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

  Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Software System 100%
  • Associative storage 99%
  • Hardware 87%
  • Computer hardware 42%
  • Application programs 35%

• A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

  Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Timing 100%
  • Unit 87%
  • Computer hardware 74%
  • Configuration 66%
  • Architecture 46%
  2 Citations (Scopus)

• A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security 100%
  • Hardware 95%
  • Machine Learning 85%
  • Machine learning 57%
  • Support Vector Machine 32%
  24 Citations (Scopus)

• A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

  Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security 100%
  • Hardware 95%
  • Scoring 93%
  • Benchmark 35%
  • Integrated circuit design 12%
  8 Citations (Scopus)

• A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

  Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Energy Levels 100%
  • Electron energy levels 96%
  • Energy 44%
  • High-level Synthesis 32%
  • Delay Time 22%

• A high-level synthesis algorithm with inter-island distance based operation chainings for RDR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1366-1375 10 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Latency 26%
  • List Scheduling 16%
  1 Citation (Scopus)

• A high-level synthesis system for digital signal processing based on data-flow graph enumeration

  Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • Digital Signal Processing 72%
  • Data flow graphs 72%
  • Flow Graphs 68%
  • Data Flow 67%

• A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

  Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

  Research output: Contribution to journal › Article › peer-review

  • Internet of things 100%
  • Power Consumption 77%
  • Power Analysis 66%
  • Energy Consumption 36%
  • Electric power utilization 35%
  1 Citation (Scopus)

• A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches

  Tawada, M., Yanagisawa, M. & Togawa, N., 2013 Jun, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Cache 100%
  • Simulator 86%
  • High Speed 82%
  • Data structures 55%
  • Trace 54%

• A locality-aware hybrid NoC configuration algorithm utilizing the communication volume among IP cores

  Lee, S., Yanagisawa, M. & Togawa, N., 2012 Sep, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 9, p. 1538-1549 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Network on chip 100%
  • Intellectual property core 63%
  • Locality 59%
  • Network-on-chip 56%
  • Communication 45%
  1 Citation (Scopus)

• A low power soft error hardened latch with schmitt-trigger-based C-Element

  Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1025-1034 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Trigger 63%
  • Power Consumption 38%
  • Electric power utilization 17%
  • Double Sampling 15%
  • Design 14%
  4 Citations (Scopus)

• A multiple cyclic-route generation method with route length constraint considering point-of-interests

  Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Reference Point 100%
  • User Preferences 71%
  • Search Methods 45%

• An algorithm and a flexible architecture for fast block-matching motion estimation

  Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Block Matching 100%
  • Motion Estimation 82%
  • Architecture 55%
  • Motion estimation 53%
  • Hardware Architecture 38%
  3 Citations (Scopus)

• An area/time optimizing algorithm in high-level synthesis of control-based hardwares

  Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 May, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Hardware 61%
  • Hardware Architecture 29%
  • Computer hardware 29%
  1 Citation (Scopus)

• An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

  Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1406-1418 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Timing 100%
  • Prediction Error 98%
  • Networks (circuits) 46%
  • Checkpoint 30%
  • Min-cut 12%
  3 Citations (Scopus)

• An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis 100%
  • Energy Efficient 82%
  • High level synthesis 64%
  • Clocks 43%
  • Design 31%
  1 Citation (Scopus)

• An FPGA implementation method based on distributed-register architectures

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb, In: IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Field programmable gate arrays (FPGA) 100%
  • Networks (circuits) 67%
  • High level synthesis 26%

• An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications

  Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Field Programmable Gate Array 100%
  • Look-up Table 92%
  • System Design 83%
  • Table lookup 76%
  • Layout 73%

• An ising machine-based solver for visiting-route recommendation problems in amusement parks

  MUKASA, Y., WAKAIZUMI, T., TANAKA, S. & TOGAWA, N., 2021, In: IEICE Transactions on Information and Systems. E104D, 10, p. 1592-1600 9 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Ising model 100%
  • Combinatorial optimization 69%
  • Simulated annealing 63%

• An l1 cache design space exploration system for embedded applications

  Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Design Space Exploration 100%
  • Cache 67%
  • Data storage equipment 27%
  • Embedded systems 21%
  • Configuration 10%

• A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

  Togawa, N., Sato, M. & Ohtsuki, T., 1997 Oct, In: Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

  Research output: Contribution to journal › Article › peer-review

  • Field programmable gate arrays (FPGA) 100%
  • Networks (circuits) 67%

• Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

  Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Delay Estimation 100%
  • Digital Signal Processor 100%
  • Hardware 63%
  • Digital signal processors 57%
  • Software 47%
  4 Citations (Scopus)

• A relaxed bit-write-reducing and error-correcting code for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Jul, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.

  Research output: Contribution to journal › Article › peer-review

  • Error-correcting Codes 100%
  • Data storage equipment 51%
  • Crosstalk 27%
  • Systematic Error 23%
  • Error Correction 22%

• A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

  Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Simulator 100%
  • Generator 56%
  • Simulators 56%
  • Computer hardware 45%
  • Unit 42%

• A robust indoor/outdoor detection method based on spatial and temporal features of sparse GPS measured positions

  Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 6, p. 860-865 6 p.

  Research output: Contribution to journal › Article › peer-review

  • Global positioning system 100%
  • Random forests 61%
  • Classifiers 41%
  • Random Forest 37%
  • Classifier 28%
  1 Citation (Scopus)

• A route recommendation method considering individual user’s preferences by monte-carlo tree search and its evaluations

  Ishizaki, Y., Koyama, Y., Takayama, T. & Togawa, N., 2021, In: Journal of information processing. 29, p. 81-92 12 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Smartphones 100%
  • Support vector machines 86%
  1 Citation (Scopus)

• A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

  Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Nov 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Landmarks 100%
  • Lighting 60%
  • Safety 34%
  • Count 26%
  • Algorithm Design 20%
  3 Citations (Scopus)

• A scan-based attack based on discriminators for AES cryptosystems

  Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Discriminators 100%
  • Cryptosystem 94%
  • Attack 81%
  • Cryptography 72%
  • Chain 50%
  43 Citations (Scopus)

• A secure test technique for pipelined advanced encryption standard

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In: IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

  Research output: Contribution to journal › Article › peer-review

  • Cryptography 100%
  • Failure analysis 52%
  • Testing 31%
  3 Citations (Scopus)

• A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

  Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In: IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Decomposition 100%
  • Set theory 88%
  1 Citation (Scopus)

• A simultaneous placement and global routing algorithm for FPGAs with power optimization

  Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Jan 1, In: Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Routing algorithms 100%
  • Field programmable gate arrays (FPGA) 80%
  • Electric power utilization 24%
  • Networks (circuits) 18%

• A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints

  Togawa, N., Sato, M. & Ohtsuki, T., 1996 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Field Programmable Gate Array 100%
  • Routing Algorithm 90%
  • Placement 73%
  • Routing algorithms 64%
  • Routing 49%

• A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 May 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Location Estimation 100%
  • Positioning 83%
  • Global positioning system 52%
  • Mobile Devices 18%
  • Battery 14%
  2 Citations (Scopus)