Nozomu Togawa

Research output

Research output per year 1994 2021

• 1078 Citations
• 16 h-Index
• 135 Conference contribution
• 106 Article
• 14 Paper
• 6 Conference article
• 9 More
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

Research output per year

Research output per year

Search results

• Article

  A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • High level synthesis
  • Architecture
  • Controller
  • Controllers

• A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Code Generation
  • Error-correcting Codes
  • Clustering
  • Data storage equipment
  • Crosstalk
  1 Citation (Scopus)

• A capacitance measurement device for running hardware devices and its evaluations

  Nishizawa, M., Hasegawa, K. & Togawa, N., 2020 Sep 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E103A, 9, p. 1018-1027 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Capacitance measurement
  • Capacitance
  • Hardware
  • Evaluation
  • Computer hardware

• A circuit partitioning algorithm with path delay constraints for multi-FPGA systems

  Togawa, N., 1997 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Field Programmable Gate Array
  • Critical Path
  • Partitioning
  • Field programmable gate arrays (FPGA)
  • Chip
  3 Citations (Scopus)

• A delay-variation-aware high-level synthesis algorithm for RDR architectures

  Hagio, Y., Yanagisawa, M. & Togawa, N., 2014, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 81-90 10 p.

  Research output: Contribution to journal › Article › peer-review

  • High level synthesis
  • Scheduling
  • Silicon
  5 Citations (Scopus)

• A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

  Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Logic
  • Boolean Networks
  • Minimise
  • Look-up Table
  • Table lookup
  1 Citation (Scopus)

• A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

  Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In: IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Cryptography
  • Computer hardware

• A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Scheduling Algorithm
  • Fast Algorithm
  • Scheduling algorithms
  • Synthesis
  • Connectivity

• A fast selector-based subtract-multiplication unit and its application to butterfly unit

  Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Fast Fourier transforms
  1 Citation (Scopus)

• A fastweighted adder by reducing partial product for reconstruction in super-resolution

  Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Adders
  • Optical resolving power
  • Image resolution
  • Time delay
  • Costs

• A fault-secure high-level synthesis algorithm for RDR architectures

  Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

  Research output: Contribution to journal › Article › peer-review

  • High level synthesis
  • Scheduling
  • Error detection
  12 Citations (Scopus)

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • Leakage
  • High level synthesis
  • Bias voltage
  • Compensation and Redress

• A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

  Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • Field Programmable Gate Array
  • High level synthesis
  • Field programmable gate arrays (FPGA)
  • Design
  2 Citations (Scopus)

• A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

  Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019, In: IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Ising model
  • Annealing
  • Combinatorial optimization
  • Ground state
  • Chain length
  2 Citations (Scopus)

• A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

  Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Apr, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware
  • Software
  • Banks
  • Computer hardware
  • Unit

• A hard ware/S oft ware cosynthesis system for digital signal processor cores

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.

  Research output: Contribution to journal › Article › peer-review

  • Digital Signal Processor
  • Digital signal processors
  • Application programs
  • Hardware
  • kernel
  16 Citations (Scopus)

• A hardware/software cosynthesis system for digital signal processor cores with two types of register files

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Digital Signal Processor
  • Software System
  • Hardware
  • Digital signal processors
  • Digital signal processing
  9 Citations (Scopus)

• A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

  Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Software System
  • Associative storage
  • Hardware
  • Computer hardware
  • Application programs

• A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

  Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

  Research output: Contribution to journal › Article › peer-review

  • Timing
  • Unit
  • Computer hardware
  • Configuration
  • Architecture
  2 Citations (Scopus)

• A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security
  • Hardware
  • Machine Learning
  • Machine learning
  • Support Vector Machine
  16 Citations (Scopus)

• A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

  Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Hardware security
  • Hardware
  • Scoring
  • Benchmark
  • Integrated circuit design
  7 Citations (Scopus)

• A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

  Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Energy Levels
  • Electron energy levels
  • Energy
  • High-level Synthesis
  • Delay Time

• A high-level synthesis algorithm with inter-island distance based operation chainings for RDR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1366-1375 10 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • High level synthesis
  • Architecture
  • List Scheduling
  • Interconnection
  1 Citation (Scopus)

• A high-level synthesis system for digital signal processing based on data-flow graph enumeration

  Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • Data flow graphs
  • Flow Graphs
  • Data Flow
  • High level synthesis

• A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

  Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

  Research output: Contribution to journal › Article › peer-review

  • Internet of things
  • Power Consumption
  • Power Analysis
  • Energy Consumption
  • Noise Reduction
  1 Citation (Scopus)

• A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches

  Tawada, M., Yanagisawa, M. & Togawa, N., 2013 Jun, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Cache
  • Simulator
  • High Speed
  • Data structures
  • Trace

• A locality-aware hybrid NoC configuration algorithm utilizing the communication volume among IP cores

  Lee, S., Yanagisawa, M. & Togawa, N., 2012 Sep, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 9, p. 1538-1549 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Network on chip
  • Intellectual property core
  • Locality
  • Network-on-chip
  • Communication
  1 Citation (Scopus)

• A low power soft error hardened latch with schmitt-trigger-based C-Element

  Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1025-1034 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Soft Error
  • Trigger
  • Power Consumption
  • Electric power utilization
  • Double Sampling
  2 Citations (Scopus)

• A multiple cyclic-route generation method with route length constraint considering point-of-interests

  Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Reference Point
  • User Preferences
  • Search Methods

• An algorithm and a flexible architecture for fast block-matching motion estimation

  Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Block Matching
  • Motion Estimation
  • Architecture
  • Motion estimation
  • Hardware Architecture
  3 Citations (Scopus)

• An area/time optimizing algorithm in high-level synthesis of control-based hardwares

  Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 May, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • High level synthesis
  • Hardware
  • Hardware Architecture
  • Computer hardware
  1 Citation (Scopus)

• An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

  Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1406-1418 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Timing
  • Prediction Error
  • Insertion
  • Networks (circuits)
  • Checkpoint
  3 Citations (Scopus)

• An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • Energy Efficient
  • High level synthesis
  • Clocks
  • Design
  1 Citation (Scopus)

• An FPGA implementation method based on distributed-register architectures

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb, In: IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Field programmable gate arrays (FPGA)
  • Networks (circuits)
  • High level synthesis

• An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications

  Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Field Programmable Gate Array
  • Look-up Table
  • Reconfiguration
  • System Design
  • Table lookup

• An l1 cache design space exploration system for embedded applications

  Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Design Space Exploration
  • Cache
  • Data storage equipment
  • Embedded systems
  • Configuration

• A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

  Togawa, N., Sato, M. & Ohtsuki, T., 1997 Oct, In: Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

  Research output: Contribution to journal › Article › peer-review

  • Field programmable gate arrays (FPGA)
  • Networks (circuits)

• Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

  Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Delay Estimation
  • Digital Signal Processor
  • Hardware
  • Digital signal processors
  • Software
  4 Citations (Scopus)

• A relaxed bit-write-reducing and error-correcting code for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Jul, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.

  Research output: Contribution to journal › Article › peer-review

  • Error-correcting Codes
  • Data storage equipment
  • Crosstalk
  • Systematic Error
  • Error Correction

• A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

  Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

  Research output: Contribution to journal › Article › peer-review

  • Simulator
  • Generator
  • Simulators
  • Computer hardware
  • Unit

• A robust indoor/outdoor detection method based on spatial and temporal features of sparse GPS measured positions

  Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 6, p. 860-865 6 p.

  Research output: Contribution to journal › Article › peer-review

  • Global positioning system
  • Classifiers
  • Random Forest
  • Classifier
  • Machine learning
  1 Citation (Scopus)

• A route recommendation method considering individual user’s preferences by monte-carlo tree search and its evaluations

  Ishizaki, Y., Koyama, Y., Takayama, T. & Togawa, N., 2021, In: Journal of information processing. 29, p. 81-92 12 p.

  Research output: Contribution to journal › Article › peer-review

  Open Access

  • Smartphones
  • Support vector machines

• A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

  Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Nov 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

  Research output: Contribution to journal › Article › peer-review

  • Landmarks
  • Lighting
  • Safety
  • Count
  • Algorithm Design
  3 Citations (Scopus)

• A scan-based attack based on discriminators for AES cryptosystems

  Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Discriminators
  • Cryptosystem
  • Attack
  • Cryptography
  • Chain
  35 Citations (Scopus)

• A secure test technique for pipelined advanced encryption standard

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In: IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

  Research output: Contribution to journal › Article › peer-review

  • Cryptography
  • Failure analysis
  • Testing
  3 Citations (Scopus)

• A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

  Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In: IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Decomposition
  • Set theory
  1 Citation (Scopus)

• A simultaneous placement and global routing algorithm for FPGAs with power optimization

  Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Jan 1, In: Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

  Research output: Contribution to journal › Article › peer-review

  • Routing algorithms
  • Field programmable gate arrays (FPGA)
  • Electric power utilization
  • Networks (circuits)

• A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints

  Togawa, N., Sato, M. & Ohtsuki, T., 1996 Jan 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.

  Research output: Contribution to journal › Article › peer-review

  • Field Programmable Gate Array
  • Routing Algorithm
  • Placement
  • Routing algorithms
  • Routing

• A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 May 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Location Estimation
  • Positioning
  • Global positioning system
  • Mobile Devices
  • Battery
  2 Citations (Scopus)

• A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

  Kawamura, K., Yanagisawa, M. & Togawa, N., 2013 Jan, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 1, p. 312-321 10 p.

  Research output: Contribution to journal › Article › peer-review

  • High-level Synthesis
  • High level synthesis
  • Architecture
  • Chip
  • Energy Consumption
  1 Citation (Scopus)