Nozomu Togawa &ndash; Research Output

Article

A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

Terada, K., Yanagisawa, M. & Togawa, N., 2017 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

Research output: Contribution to journal › Article

High-level Synthesis

Controller

Controllers

Unit

Hardware Design

1 Citation (Scopus)

A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

Research output: Contribution to journal › Article

Code Generation

Error-correcting Codes

Clustering

Data storage equipment

One to many

3 Citations (Scopus)

A circuit partitioning algorithm with path delay constraints for multi-FPGA systems

Togawa, N., 1997, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.

Research output: Contribution to journal › Article

Field Programmable Gate Array

Critical Path

Field programmable gate arrays (FPGA)

Partitioning

Path

5 Citations (Scopus)

A delay-variation-aware high-level synthesis algorithm for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2014, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 81-90 10 p.

Research output: Contribution to journal › Article

Scheduling

High level synthesis

Silicon

1 Citation (Scopus)

A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.

Research output: Contribution to journal › Article

Logic

Boolean Networks

Minimise

Table lookup

Look-up Table

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

Research output: Contribution to journal › Article

Cryptography

Hardware

A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.

Research output: Contribution to journal › Article

Scheduling algorithms

Scheduling Algorithm

Fast Algorithm

Synthesis

Connectivity

1 Citation (Scopus)

A fast selector-based subtract-multiplication unit and its application to butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

Research output: Contribution to journal › Article

Fast Fourier transforms

A fastweighted adder by reducing partial product for reconstruction in super-resolution

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

Research output: Contribution to journal › Article

Adders

Optical resolving power

Image resolution

Costs

Time delay

12 Citations (Scopus)

A fault-secure high-level synthesis algorithm for RDR architectures

Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

Research output: Contribution to journal › Article

Scheduling

Error detection

High level synthesis

A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

Igawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

Research output: Contribution to journal › Article

High-level Synthesis

Bias voltage

Leakage

Data flow graphs

Energy

2 Citations (Scopus)

A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

Research output: Contribution to journal › Article

High-level Synthesis

Field Programmable Gate Array

Field programmable gate arrays (FPGA)

Module

Costs

A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019 Jan 1, In : IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

Research output: Contribution to journal › Article

Open Access

Ising model

Combinatorial optimization

Annealing

Chain length

Ground state

A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Apr, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.

Research output: Contribution to journal › Article

Hardware

Software

Unit

Application programs

Cycle

16 Citations (Scopus)

A hard ware/S oft ware cosynthesis system for digital signal processor cores

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.

Research output: Contribution to journal › Article

Digital Signal Processor

Digital signal processors

Application programs

kernel

Computer hardware

9 Citations (Scopus)

A hardware/software cosynthesis system for digital signal processor cores with two types of register files

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.

Research output: Contribution to journal › Article

Digital Signal Processor

Digital signal processors

Digital signal processing

Application programs

Software System

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

Research output: Contribution to journal › Article

Associative storage

Software System

Hardware

Application programs

Memory Function

2 Citations (Scopus)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

Research output: Contribution to journal › Article

Hardware/software Partitioning

Hardware

Unit

Timing

Configuration

9 Citations (Scopus)

A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

Research output: Contribution to journal › Article

Learning systems

Machine Learning

Hardware

Support vector machines

Neural networks

5 Citations (Scopus)

A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

Research output: Contribution to journal › Article

Scoring

Hardware

Benchmark

Classify

Outsourcing

A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.

Research output: Contribution to journal › Article

Energy Levels

Electron energy levels

Energy

High-level Synthesis

Delay Time

1 Citation (Scopus)

A high-level synthesis algorithm with inter-island distance based operation chainings for RDR architectures

Terada, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1366-1375 10 p.

Research output: Contribution to journal › Article

High-level Synthesis

Latency

List Scheduling

Interconnection

Scheduling

A high-level synthesis system for digital signal processing based on data-flow graph enumeration

Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.

Research output: Contribution to journal › Article

Data flow graphs

High-level Synthesis

Flow Graphs

Digital signal processing

Data Flow

A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

Research output: Contribution to journal › Article

Power Analysis

Power Consumption

Electric power utilization

Noise Reduction

Noise abatement

A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches

Tawada, M., Yanagisawa, M. & Togawa, N., 2013 Jun, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.

Research output: Contribution to journal › Article

Cache

Data structures

Simulator

High Speed

Simulators

1 Citation (Scopus)

A locality-aware hybrid NoC configuration algorithm utilizing the communication volume among IP cores

Lee, S., Yanagisawa, M. & Togawa, N., 2012 Sep, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 9, p. 1538-1549 12 p.

Research output: Contribution to journal › Article

Locality

Configuration

Communication

Hierarchical Networks

Multimedia Applications

A low power soft error hardened latch with schmitt-trigger-based C-Element

Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1025-1034 10 p.

Research output: Contribution to journal › Article

Soft Error

Trigger

Power Consumption

Electric power utilization

Double Sampling

A multiple cyclic-route generation method with route length constraint considering point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

Research output: Contribution to journal › Article

Reference Point

User Preferences

Search Methods

3 Citations (Scopus)

An algorithm and a flexible architecture for fast block-matching motion estimation

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.

Research output: Contribution to journal › Article

Block Matching

Motion Estimation

Motion estimation

Hardware Architecture

Computer hardware description languages

1 Citation (Scopus)

An area/time optimizing algorithm in high-level synthesis of control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.

Research output: Contribution to journal › Article

High-level Synthesis

Hardware

Application programs

Graph in graph theory

Hardware Architecture

3 Citations (Scopus)

An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1406-1418 13 p.

Research output: Contribution to journal › Article

Prediction Error

Insertion

Timing

Networks (circuits)

Checkpoint

1 Citation (Scopus)

An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.

Research output: Contribution to journal › Article

High-level Synthesis

Energy Efficient

Clocks

Interconnect

Energy Saving

A new hardware/software partitioning algorithm for DSP processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2802-2807 6 p.

Research output: Contribution to journal › Article

Hardware/software Partitioning

Hardware

Unit

Digital Signal Processor

Digital signal processors

An FPGA implementation method based on distributed-register architectures

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

Research output: Contribution to journal › Article

Open Access

Field programmable gate arrays (FPGA)

Networks (circuits)

An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.

Research output: Contribution to journal › Article

Table lookup

Look-up Table

Reconfiguration

Field Programmable Gate Array

System Design

An l1 cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.

Research output: Contribution to journal › Article

Design Space Exploration

Cache

Data storage equipment

Embedded systems

Configuration

A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1997 Oct, In : Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

Research output: Contribution to journal › Article

Field programmable gate arrays (FPGA)

Networks (circuits)

4 Citations (Scopus)

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 Nov, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

Research output: Contribution to journal › Article

Delay Estimation

Digital Signal Processor

Digital signal processors

Hardware

Software

A relaxed bit-write-reducing and error-correcting code for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.

Research output: Contribution to journal › Article

Error-correcting Codes

Data storage equipment

Systematic Error

Crosstalk

Error Correction

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

Research output: Contribution to journal › Article

Simulator

Simulators

Generator

Hardware

Application programs

1 Citation (Scopus)

A robust indoor/outdoor detection method based on spatial and temporal features of sparse GPS measured positions

Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 6, p. 860-865 6 p.

Research output: Contribution to journal › Article

Global positioning system

Classifiers

Random Forest

Learning systems

Classify

1 Citation (Scopus)

A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 Nov 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

Research output: Contribution to journal › Article

Landmarks

Lighting

Count

Safety

Algorithm Design

29 Citations (Scopus)

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

Research output: Contribution to journal › Article

Discriminators

Cryptosystem

Cryptography

Attack

Networks (circuits)

3 Citations (Scopus)

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Mar, In : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

Research output: Contribution to journal › Article

Cryptography

Failure analysis

Testing

1 Citation (Scopus)

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

Research output: Contribution to journal › Article

Decomposition

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 Feb, In : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

Research output: Contribution to journal › Article

Routing algorithms

Field programmable gate arrays (FPGA)

Electric power utilization

Networks (circuits)

A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints

Togawa, N., Sato, M. & Ohtsuki, T., 1996, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.

Research output: Contribution to journal › Article

Routing algorithms

Routing Algorithm

Field Programmable Gate Array

Placement

Path

2 Citations (Scopus)

A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 May 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

Research output: Contribution to journal › Article

Location Estimation

Positioning

Global positioning system

Mobile devices

Mobile Devices

1 Citation (Scopus)

A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2013 Jan, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 1, p. 312-321 10 p.

Research output: Contribution to journal › Article

High-level Synthesis

Chip

Interconnect

Energy Consumption

Energy utilization

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

Research output: Contribution to journal › Article

Design Space Exploration

Cache

Data storage equipment

Embedded systems

Energy utilization