• 945 Citations
  • 15 h-Index
1994 …2020

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Bi-partitioning based multiplexer network for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Circuit partitioning algorithm with replication capability for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1995 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2 Citations (Scopus)
2 Citations (Scopus)

Efficient multiplexer networks for field-data extractors and their evaluations

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 Apr 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

Research output: Contribution to journalArticle

Energy-efficient high-level synthesis for HDR architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012 Aug 17, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 106-117 12 p.

Research output: Contribution to journalArticle

13 Citations (Scopus)

Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

Akasaka, H., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2014, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 74-80 7 p.

Research output: Contribution to journalArticle

Fast scheduling and allocation algorithms for entropy CODEC

Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997 Jan 1, In : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)
2 Citations (Scopus)

Floorplan-driven high-level synthesis for distributed/shared-register architectures

Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 Aug 1, In : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

Research output: Contribution to journalArticle

8 Citations (Scopus)

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
3 Citations (Scopus)
7 Citations (Scopus)
4 Citations (Scopus)

High-level power optimization based on thread partitioning

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

Research output: Contribution to journalArticle

Improved launch for higher TDF coverage with fewer test patterns

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 Aug 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

Research output: Contribution to journalArticle

7 Citations (Scopus)
14 Citations (Scopus)

Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Apr, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)

Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 Jul, In : IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Robust secure scan design against scan-based differential cryptanalysis

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

Research output: Contribution to journalArticle

19 Citations (Scopus)
Open Access
1 Citation (Scopus)

Scan-based attack against DES and Triple DES cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2013 Jul 19, In : Journal of information processing. 21, 3, p. 572-579 8 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
5 Citations (Scopus)

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

Research output: Contribution to journalArticle

48 Citations (Scopus)

Scan-based side-channel attack on the camellia block cipher using scan signatures

Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
3 Citations (Scopus)

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)
2 Citations (Scopus)

Simultaneous placement and global routing for transport-processing FPGA layout

Togawa, N., Sato, M. & Ohtsuki, T., 1996 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011 Aug 1, In : ieice electronics express. 8, 14, p. 1161-1167 7 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)
5 Citations (Scopus)

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

Research output: Contribution to journalArticle

Trojan-net classification for gate-level hardware design utilizing boundary net structures

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2020 Jul 1, In : IEICE Transactions on Information and Systems. E103D, 7, p. 1618-1622 5 p.

Research output: Contribution to journalArticle

Open Access
3 Citations (Scopus)

Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 Sep, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

Research output: Contribution to journalArticle