Research Output per year
Research Output
2019
A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing
Sun, X., Guo, Y., Liu, Z. & Kimura, S., 2019 Jan 17, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., p. 777-780 4 p. 8617854. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier
Guo, Y., Sun, H. & Kimura, S., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 2110-2115 6 p. 8650108. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering
Liu, Z., Guo, Y., Sun, X. & Kimura, S., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 545-550 6 p. 8650340. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors
Guo, Y., Sun, H., Guo, L. & Kimura, S., 2019 Jan 8, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 291-294 4 p. 8605570. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
4
Citations
(Scopus)
2018
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme
Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2018 Jan 1, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.Research output: Contribution to journal › Article
8
Citations
(Scopus)
A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC
Zhou, J., Zhou, D., Zhang, S., Kimura, S. & Goto, S., 2018 Feb 1, In : IEEE Transactions on Circuits and Systems for Video Technology. 28, 2, p. 556-560 5 p., 7577726.Research output: Contribution to journal › Article
Embedded Frame Compression for Energy-Efficient Computer Vision Systems
Guo, L., Zhou, D., Zhou, J. & Kimura, S., 2018 Apr 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8351483. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2018-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2
Citations
(Scopus)
Lossy Compression for Embedded Computer Vision Systems
Guo, L., Zhou, D., Zhou, J., Kimura, S. & Goto, S., 2018 Jul 3, (Accepted/In press) In : IEEE Access.Research output: Contribution to journal › Article
5
Citations
(Scopus)
Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA
Zhang, Z., Zhou, D., Wang, S. & Kimura, S., 2018 Feb 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 184-189 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2018-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Citation
(Scopus)
Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression
Guo, L., Zhou, D., Zhou, J. & Kimura, S., 2018 Apr 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8351094. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2018-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity
Jin, C., Sun, H. & Kimura, S., 2018 Feb 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 190-195 6 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2
Citations
(Scopus)
Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging
Ibrahim, A., Zhang, S., Angiolini, F., Arditi, M., Kimura, S., Goto, S., Thiran, J. P. & De Micheli, G., 2018 Jun 1, (Accepted/In press) In : IEEE Transactions on Biomedical Circuits and Systems.Research output: Contribution to journal › Article
2
Citations
(Scopus)
2017
A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor
Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2017 Mar, In : IEICE Transactions on Electronics. E100C, 3, p. 223-231 9 p.Research output: Contribution to journal › Article
Accelerating HEVC inter prediction with improved merge mode handling
Cheng, Z., Sun, H., Zhou, D. & Kimura, S., 2017 Feb 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 2, p. 546-554 9 p.Research output: Contribution to journal › Article
3
Citations
(Scopus)
A low-cost approximate 32-point transform architecture
Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050263Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Citation
(Scopus)
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design
Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2017 Jan, In : IEEE Journal of Solid-State Circuits. 52, 1, p. 113-126 14 p., 7736091.Research output: Contribution to journal › Article
13
Citations
(Scopus)
Distortion control and optimization for lossy embedded compression in video codec system
Guo, L., Zhou, D., Kimura, S. & Goto, S., 2017 Nov 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2416-2424 9 p.Research output: Contribution to journal › Article
Effective write-reduction method for MLC non-volatile memory
Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC
Sun, H., Zhou, D., Hu, L., Kimura, S. & Goto, S., 2017 Nov 1, In : IEEE Transactions on Multimedia. 19, 11, p. 2375-2390 16 p., 7918540.Research output: Contribution to journal › Article
4
Citations
(Scopus)
Optimization of area and power in multi-mode power gating scheme for static memory elements
Su, X. & Kimura, S., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 214-217 4 p. 7803936Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering
Yang, F., Lin, M., Sun, H. & Kimura, S., 2017 Sep 27, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-August. p. 1200-1203 4 p. 8053144Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2016
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications
Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 Feb 23, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., Vol. 59. p. 266-268 3 p. 7418009Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
19
Citations
(Scopus)
A low-power VLSI architecture for HEVC de-quantization and inverse transform
Sun, H., Zhou, D., Zhang, S. & Kimura, S., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2375-2387 13 p.Research output: Contribution to journal › Article
1
Citation
(Scopus)
CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks
Han, X., Zhou, D., Wang, S. & Kimura, S., 2016 Nov 22, Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc., p. 320-327 8 p. 7753296Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
20
Citations
(Scopus)
Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems
Guo, L., Zhou, D., Kimura, S. & Goto, S., 2016 Sep 22, 2016 IEEE International Conference on Multimedia and Expo Workshop, ICMEW 2016. Institute of Electrical and Electronics Engineers Inc., 7574759Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Citation
(Scopus)
Merge mode based fast inter prediction for HEVC
Cheng, Z., Sun, H., Zhou, D. & Kimura, S., 2016 Apr 21, 2015 Visual Communications and Image Processing, VCIP 2015. Institute of Electrical and Electronics Engineers Inc., 7457826Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Citation
(Scopus)
Power-efficient and slew-aware three dimensional gated clock tree synthesis
Lin, M., Sun, H. & Kimura, S., 2016 Nov 22, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753535Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
5
Citations
(Scopus)
2015
A bit-write reduction method based on error-correcting codes for non-volatile memories
Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
5
Citations
(Scopus)
An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder
Sun, H., Zhou, D., Zhu, J., Kimura, S. & Goto, S., 2015 Feb 27, 2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 197-200 4 p. 7051538. (2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
7
Citations
(Scopus)
An independent bandwidth reduction device for HEVC VLSI video system
Zhu, J., Guo, L., Zhou, D., Kimura, S. & Goto, S., 2015 Jul 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July. p. 609-612 4 p. 7168707Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
4
Citations
(Scopus)
ECC-Based bit-write reduction code generation for non-volatile memory
Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2494-2504 11 p.Research output: Contribution to journal › Article
2
Citations
(Scopus)
Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder
Hu, L., Sun, H., Zhou, D. & Kimura, S., 2015 Jul 28, 2015 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2015. Institute of Electrical and Electronics Engineers Inc., 7169808Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
3
Citations
(Scopus)
Low-power motion estimation processor with 3D stacked memory
Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1431-1441 11 p.Research output: Contribution to journal › Article
1
Citation
(Scopus)
2014
Fast SAO estimation algorithm and its implementation for 8K × 4K @ 120 FPS HEVC encoding
Zhu, J., Zhou, D., Kimura, S. & Goto, S., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2488-2497 10 p.Research output: Contribution to journal › Article
2
Citations
(Scopus)
Fast SAO estimation algorithm and its VLSI architecture
Zhu, J., Zhou, D., Kimura, S. & Goto, S., 2014 Jan 28, 2014 IEEE International Conference on Image Processing, ICIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 1278-1282 5 p. 7025255Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
7
Citations
(Scopus)
Foreword: Special section on VLSI design and CAD algorithms
Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 others, , 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, 1 p.Research output: Contribution to journal › Editorial
2013
An exact approach for gpc-based compressor tree synthesis
Matsunaga, T., Kimura, S. & Matsunaga, Y., 2013 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2553-2560 8 p.Research output: Contribution to journal › Article
11
Citations
(Scopus)
Controlling-value-based power gating considering controllability propagation and power-off probability
Du, Z., Jin, Y. & Kimura, S., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811909. (Proceedings of International Conference on ASIC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Dual-stage pseudo power gating with advanced clustering algorithm for gate level power optimization
Jin, Y., Dv, Z. & Kimura, S., 2013 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2568-2575 8 p.Research output: Contribution to journal › Article
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors
Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811826. (Proceedings of International Conference on ASIC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Citation
(Scopus)
Write control method for nonvolatile flip-flops based on state transition analysis
Okada, N., Nakamura, Y. & Kimura, S., 2013 Jun, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1264-1272 9 p.Research output: Contribution to journal › Article
2012
Automatic multi-stage clock gating optimization using ILP formulation
Man, X., Horiyama, T. & Kimura, S., 2012 Aug, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 8, p. 1347-1358 12 p.Research output: Contribution to journal › Article
1
Citation
(Scopus)
On gate level power optimization of combinational circuits using pseudo power gating
Jin, Y. & Kimura, S., 2012 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 12, p. 2191-2198 8 p.Research output: Contribution to journal › Article
2
Citations
(Scopus)
2011
Comparison of optimized multi-stage clock gating with structural gating approach
Man, X. & Kimura, S., 2011 Dec 1, TENCON 2011 - 2011 IEEE Region 10 Conference: Trends and Development in Converging Technology Towards 2020. p. 651-656 6 p. 6129188. (IEEE Region 10 Annual International Conference, Proceedings/TENCON).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
7
Citations
(Scopus)
High-parallel LDPC decoder with power gating design
Cui, Y., Peng, X., Jin, Y., Liu, P., Kimura, S. & Goto, S., 2011 Dec 1, Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. p. 21-24 4 p. 6157112. (Proceedings of International Conference on ASIC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Multi-operand adder synthesis targeting FPGAs
Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2579-2586 8 p.Research output: Contribution to journal › Article
10
Citations
(Scopus)
Multi-stage power gating based on controlling values of logic gates
Jin, Y. & Kimura, S., 2011 Dec 1, Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. p. 79-82 4 p. 6157127. (Proceedings of International Conference on ASIC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs
Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011 Sep 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 217-222 6 p. 5993639. (Proceedings of the International Symposium on Low Power Electronics and Design).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
13
Citations
(Scopus)
2010
Multi-operand adder synthesis on FPGAs using generalized parallel counters
Matsunaga, T., Kimura, S. & Matsunaga, Y., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 337-342 6 p. 5419871. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
8
Citations
(Scopus)
Power optimization of sequential circuits using switching activity based clock gating
Man, X., Horiyama, T. & Kimura, S., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2472-2480 9 p.Research output: Contribution to journal › Article
2
Citations
(Scopus)