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Research Output 1982 2019

  • 323 Citations
  • 10 h-Index
  • 51 Conference contribution
  • 45 Article
  • 1 Conference article
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Conference contribution
2019

A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing

Sun, X., Guo, Y., Liu, Z. & Kimura, S., 2019 Jan 17, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., p. 777-780 4 p. 8617854. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

multipliers
Digital signal processing
signal processing
high speed
products

Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier

Guo, Y., Sun, H. & Kimura, S., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 2110-2115 6 p. 8650108. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Compressors
Discrete cosine transforms
Image classification
MATLAB

Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering

Liu, Z., Guo, Y., Sun, X. & Kimura, S., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 545-550 6 p. 8650340. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compressors
Networks (circuits)
Signal to noise ratio
Signal processing
Image processing

Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors

Guo, Y., Sun, H., Guo, L. & Kimura, S., 2019 Jan 8, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 291-294 4 p. 8605570. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

multipliers
compressors
Compressors
Costs
Error compensation
2018
1 Citation (Scopus)

Embedded Frame Compression for Energy-Efficient Computer Vision Systems

Guo, L., Zhou, D., Zhou, J. & Kimura, S., 2018 Apr 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-May. 8351483

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer vision
Data storage equipment
Energy utilization
Differential pulse code modulation
Hardware

Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA

Zhang, Z., Zhou, D., Wang, S. & Kimura, S., 2018 Feb 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 184-189 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Neural networks
Cost reduction
Computer vision
Electric power utilization

Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression

Guo, L., Zhou, D., Zhou, J. & Kimura, S., 2018 Apr 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-May. 8351094

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neurons
Neural networks
Mobile devices
Artificial intelligence
Computational complexity
1 Citation (Scopus)

Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity

Jin, C., Sun, H. & Kimura, S., 2018 Feb 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 190-195 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neural networks
Field programmable gate arrays (FPGA)
Hardware
Degradation
2017
1 Citation (Scopus)

A low-cost approximate 32-point transform architecture

Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050263

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Image coding
Costs
Hardware

Effective write-reduction method for MLC non-volatile memory

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 Sep 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Durability
Embedded systems

Optimization of area and power in multi-mode power gating scheme for static memory elements

Su, X. & Kimura, S., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 214-217 4 p. 7803936

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Data storage equipment
Transistors
Trimming
Electric power utilization

Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering

Yang, F., Lin, M., Sun, H. & Kimura, S., 2017 Sep 27, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-August. p. 1200-1203 4 p. 8053144

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Tuning
Topology
Buffers
2016
15 Citations (Scopus)

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications

Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 Feb 23, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., Vol. 59. p. 266-268 3 p. 7418009

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipelines
Pixels
Data storage equipment
Inverse transforms
Image coding
14 Citations (Scopus)

CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks

Han, X., Zhou, D., Wang, S. & Kimura, S., 2016 Nov 22, Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc., p. 320-327 8 p. 7753296

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Neural networks
Data storage equipment
Bandwidth
Dynamic random access storage
1 Citation (Scopus)

Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems

Guo, L., Zhou, D., Kimura, S. & Goto, S., 2016 Sep 22, 2016 IEEE International Conference on Multimedia and Expo Workshop, ICMEW 2016. Institute of Electrical and Electronics Engineers Inc., 7574759

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Energy dissipation
Degradation
Experiments
1 Citation (Scopus)

Merge mode based fast inter prediction for HEVC

Cheng, Z., Sun, H., Zhou, D. & Kimura, S., 2016 Apr 21, 2015 Visual Communications and Image Processing, VCIP 2015. Institute of Electrical and Electronics Engineers Inc., 7457826

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Image coding
Costs
Computational complexity
4 Citations (Scopus)

Power-efficient and slew-aware three dimensional gated clock tree synthesis

Lin, M., Sun, H. & Kimura, S., 2016 Nov 22, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753535

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Trees (mathematics)
Clocks
Topology
2015
5 Citations (Scopus)

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error-correcting Codes
Reduction Method
Data storage equipment
Cell
Energy
5 Citations (Scopus)

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder

Sun, H., Zhou, D., Zhu, J., Kimura, S. & Goto, S., 2015 Feb 27, 2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 197-200 4 p. 7051538

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Hardware
Costs
Discrete cosine transforms
Static random access storage
1 Citation (Scopus)

An independent bandwidth reduction device for HEVC VLSI video system

Zhu, J., Guo, L., Zhou, D., Kimura, S. & Goto, S., 2015 Jul 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July. p. 609-612 4 p. 7168707

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bandwidth
Data storage equipment
3 Citations (Scopus)

Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder

Hu, L., Sun, H., Zhou, D. & Kimura, S., 2015 Jul 28, 2015 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2015. Institute of Electrical and Electronics Engineers Inc., 7169808

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Image coding
Hardware
Image compression
Costs
Computational complexity
2014
6 Citations (Scopus)

Fast SAO estimation algorithm and its VLSI architecture

Zhu, J., Zhou, D., Kimura, S. & Goto, S., 2014 Jan 28, 2014 IEEE International Conference on Image Processing, ICIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 1278-1282 5 p. 7025255

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Statistics
2013

Controlling-value-based power gating considering controllability propagation and power-off probability

Du, Z., Jin, Y. & Kimura, S., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811909

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllability
Leakage currents
1 Citation (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811826

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Energy utilization
Data storage equipment
Memory architecture
2011
7 Citations (Scopus)

Comparison of optimized multi-stage clock gating with structural gating approach

Man, X. & Kimura, S., 2011, IEEE Region 10 Annual International Conference, Proceedings/TENCON. p. 651-656 6 p. 6129188

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Binary decision diagrams
Networks (circuits)

High-parallel LDPC decoder with power gating design

Cui, Y., Peng, X., Jin, Y., Liu, P., Kimura, S. & Goto, S., 2011, Proceedings of International Conference on ASIC. p. 21-24 4 p. 6157112

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Engines
Processing
Energy dissipation
Networks (circuits)

Multi-stage power gating based on controlling values of logic gates

Jin, Y. & Kimura, S., 2011, Proceedings of International Conference on ASIC. p. 79-82 4 p. 6157127

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic gates
11 Citations (Scopus)

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 217-222 6 p. 5993639

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Compressors
Field programmable gate arrays (FPGA)
Inductive logic programming (ILP)
Application specific integrated circuits
2010
8 Citations (Scopus)

Multi-operand adder synthesis on FPGAs using generalized parallel counters

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 337-342 6 p. 5419871

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Field programmable gate arrays (FPGA)
Application specific integrated circuits
Hardware
2008
1 Citation (Scopus)

Synthesis of parallel prefix adders considering switching activities

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 404-409 6 p. 4751892

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Thermodynamic properties
Dynamic programming
Costs
Experiments
2006
14 Citations (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 653-658 6 p. 1594760

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cost reduction
Fans
Data compression
Product design
Costs
10 Citations (Scopus)

Transition-based coverage estimation for symbolic model checking

Xu, X., Kimura, S., Horikawa, K. & Tsuchiya, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 1-6 6 p. 1594636

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Network protocols
2005
1 Citation (Scopus)

A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Okada, M., Hiramatsu, T., Nakajima, H., Ozone, M., Hirase, K. & Kimura, S., 2005, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. Vol. 2005. 1420005

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Processing

Duplicated register file design for embedded simultaneous multithreading microprocessor

Chengjie, Z., Imai, S. & Kimura, S., 2005, ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1. p. 160-163 4 p. 1611275

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Microprocessor chips
Costs
17 Citations (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. Vol. 2005. p. 386-389 4 p. 1575460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Discrete Fourier transforms
Hardware
7 Citations (Scopus)

Transition traversal coverage estimation for symbolic model checking

Xu, X., Kimura, S., Horikawa, K. & Tsuchiya, T., 2005, Proceedings - Third ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'05. Vol. 2005. p. 259-260 2 p. 1487932

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
1 Citation (Scopus)

Transition traversal coverage estimation for symbolic model checking

Xu, X., Kimura, S., Horikawa, K. & Tsuchiya, T., 2005, ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 2. p. 850-853 4 p. 1611460

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Semantics
Costs
2004
2 Citations (Scopus)

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asian Test Symposium. p. 432-437 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coloring
Heuristic algorithms
Electric power utilization
System-on-chip
14 Citations (Scopus)

Minimization of fractional wordlength on fixed-point conversion for high-level synthesis

Doi, N., Horiyama, T., Nakanishi, M. & Kimura, S., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 80-85 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data flow graphs
High level languages
Nonlinear programming
Hardware
High level synthesis
1 Citation (Scopus)

Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. Vol. 2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data compression
Glossaries
Synchronization
Costs
System-on-chip
2003
15 Citations (Scopus)

An on-chip high speed serial communication method based on independent ring oscillators

Kimura, S., Hayakawa, T., Horiyama, T., Nakanishi, M. & Watanabe, K., 2003, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Fujino, L. C., Grabel, A., Jeager, D. & Smith, K. C. (eds.).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Communication
Data transfer
2002
10 Citations (Scopus)

Folding of logic functions and its application to look up table compaction

Kimura, S., Horiyama, T., Nakanishi, M. & Kajihara, H., 2002, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 694-697 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Adders
Data storage equipment
Hardware
Networks (circuits)
2001

A real-time 64-monosyllable recognition LSI with learning mechanism

Nakamura, K., Zhu, Q., Maruoka, S., Horiyama, T., Kimura, S. & Watanabe, K., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 31-32 2 p. 913274

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hidden Markov models
Networks (circuits)
5 Citations (Scopus)

Speech recognition chip for monosyllables

Nakamura, K., Zhu, Q., Maruoka, S., Horiyama, T., Kimura, S. & Watanabe, K., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 396-399 4 p. 913339

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Speech recognition
Networks (circuits)
Hidden Markov models
2000

An application specific Java processor with reconfigurabilities

Kimura, S., Kida, H., Takagi, K., Abematsu, T. & Watanabe, K., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 25-26 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipelines
2 Citations (Scopus)

Multi-clock path analysis using propositional satisfiability

Nakamura, K., Maruoka, S., Kimura, S. & Watanabe, K., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 81-86 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Networks (circuits)
1998
11 Citations (Scopus)

Waiting false path analysis of sequential logic circuits for performance optimization

Nakamura, K., Takagi, K., Kimura, S. & Watanabe, K., 1998, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. Yasuura, H. & White, J. (eds.). IEEE Comp Soc, p. 392-395 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sequential circuits
Clocks
Networks (circuits)
Time delay
1997
2 Citations (Scopus)

Hardware/software codesign method for a general purpose reconfigurable co-processor

Kimura, S., Yukishita, M., Itou, Y., Nagoya, A., Hirao, M. & Watanabe, K., 1997, Hardware/Software Codesign - Proceedings of the International Workshop. Anon (ed.). p. 147-151 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer systems
System buses
Dynamic mechanical analysis
Field programmable gate arrays (FPGA)
Hardware
1995
7 Citations (Scopus)

Residue BDD and its application to the verification of arithmetic circuits

Kimura, S., 1995, Proceedings - Design Automation Conference. Anon (ed.). IEEE, p. 542-545 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Explosions
Specifications
1992

Precise timing verification of logic circuits under combined delay model

Kimura, S., Kashima, S. & Haneda, H., 1992, IEEE/ACM International Conference on Computer-Aided Design. Los Alamitos, CA, United States: Publ by IEEE, p. 526-529 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic circuits
Networks (circuits)
Time delay
Hazards