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Research Output 1982 2019

  • 323 Citations
  • 10 h-Index
  • 51 Conference contribution
  • 45 Article
  • 1 Conference article
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Article
2018
1 Citation (Scopus)

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme

Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2018 Jan 1, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Discrete cosine transforms
Adders
Image coding
Signal processing
Electric power utilization

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC

Zhou, J., Zhou, D., Zhang, S., Kimura, S. & Goto, S., 2018 Feb 1, In : IEEE Transactions on Circuits and Systems for Video Technology. 28, 2, p. 556-560 5 p., 7577726.

Research output: Contribution to journalArticle

Bins
Clocks
Image coding
Decoding
Entropy
1 Citation (Scopus)

Lossy Compression for Embedded Computer Vision Systems

Guo, L., Zhou, D., Zhou, J., Kimura, S. & Goto, S., 2018 Jul 3, (Accepted/In press) In : IEEE Access.

Research output: Contribution to journalArticle

Computer vision
Data storage equipment
Energy utilization
Differential pulse code modulation
Hardware

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging

Ibrahim, A., Zhang, S., Angiolini, F., Arditi, M., Kimura, S., Goto, S., Thiran, J. P. & De Micheli, G., 2018 Jun 1, (Accepted/In press) In : IEEE Transactions on Biomedical Circuits and Systems.

Research output: Contribution to journalArticle

Ultrasonics
Imaging techniques
Image sensors
Field programmable gate arrays (FPGA)
Telemedicine
2017

A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor

Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2017 Mar 1, In : IEICE Transactions on Electronics. E100C, 3, p. 223-231 9 p.

Research output: Contribution to journalArticle

Motion estimation
Data storage equipment
Memory architecture
Silicon
Clocks
1 Citation (Scopus)

Accelerating HEVC inter prediction with improved merge mode handling

Cheng, Z., Sun, H., Zhou, D. & Kimura, S., 2017 Feb 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 2, p. 546-554 9 p.

Research output: Contribution to journalArticle

Coding
Prediction
Unit
Average-case Complexity
Early Termination

Distortion control and optimization for lossy embedded compression in video codec system

Guo, L., Zhou, D., Kimura, S. & Goto, S., 2017 Nov 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2416-2424 9 p.

Research output: Contribution to journalArticle

Compression
Optimization
Traffic
Data storage equipment
External Memory
3 Citations (Scopus)

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC

Sun, H., Zhou, D., Hu, L., Kimura, S. & Goto, S., 2017 Nov 1, In : IEEE Transactions on Multimedia. 19, 11, p. 2375-2390 16 p., 7918540.

Research output: Contribution to journalArticle

Image coding
Throughput
Hardware
Logic gates
Cost functions
2016
1 Citation (Scopus)

A low-power VLSI architecture for HEVC de-quantization and inverse transform

Sun, H., Zhou, D., Zhang, S. & Kimura, S., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2375-2387 13 p.

Research output: Contribution to journalArticle

VLSI Architecture
Inverse transforms
Quantization
Transform
Data storage equipment
10 Citations (Scopus)

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 Nov 4, (Accepted/In press) In : IEEE Journal of Solid-State Circuits.

Research output: Contribution to journalArticle

Image coding
Pipelines
Throughput
Data storage equipment
Energy efficiency
2015
2 Citations (Scopus)
Code Generation
Data storage equipment
Error-correcting Codes
Energy
Static random access storage
1 Citation (Scopus)

Low-power motion estimation processor with 3D stacked memory

Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1431-1441 11 p.

Research output: Contribution to journalArticle

Motion Estimation
Motion estimation
Die
Data storage equipment
Image coding
2014
2 Citations (Scopus)

Fast SAO estimation algorithm and its implementation for 8K × 4K @ 120 FPS HEVC encoding

Zhu, J., Zhou, D., Kimura, S. & Goto, S., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2488-2497 10 p.

Research output: Contribution to journalArticle

Video Coding
Estimation Algorithms
Image coding
High Efficiency
Encoding

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 others, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

Research output: Contribution to journalArticle

2013
10 Citations (Scopus)

An exact approach for gpc-based compressor tree synthesis

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2013, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2553-2560 8 p.

Research output: Contribution to journalArticle

Compressor
Adders
Compressors
Synthesis
Inductive logic programming (ILP)
Signal Control
Clustering algorithms
Clustering Algorithm
Optimization
Power Method

Write control method for nonvolatile flip-flops based on state transition analysis

Okada, N., Nakamura, Y. & Kimura, S., 2013 Jun, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1264-1272 9 p.

Research output: Contribution to journalArticle

Flip flop circuits
State Transition
Flip
Clocks
Electric power utilization
2012
1 Citation (Scopus)

Automatic multi-stage clock gating optimization using ILP formulation

Man, X., Horiyama, T. & Kimura, S., 2012 Aug, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 8, p. 1347-1358 12 p.

Research output: Contribution to journalArticle

Integer Linear Programming
Linear programming
Clocks
Signal Control
Optimization
2 Citations (Scopus)
Combinatorial circuits
Electric power utilization
Power Consumption
Optimization
Delay circuits
2011
9 Citations (Scopus)

Multi-operand adder synthesis targeting FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2579-2586 8 p.

Research output: Contribution to journalArticle

Adders
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Synthesis
Application specific integrated circuits
2010
2 Citations (Scopus)

Power optimization of sequential circuits using switching activity based clock gating

Man, X., Horiyama, T. & Kimura, S., 2010 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2472-2480 9 p.

Research output: Contribution to journalArticle

Circuit Switching
Sequential circuits
Signal Control
Clocks
Optimization
2009
Prototyping
Assertion
Field Programmable Gate Array
Shift registers
Automata

Framework for parallel prefix adder synthesis considering switching activities

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2009, In : IPSJ Transactions on System LSI Design Methodology. 2, p. 212-221 10 p.

Research output: Contribution to journalArticle

Adders
Thermodynamic properties
Dynamic programming
Costs
Binary decision diagrams

Message from technical program committee

Tsay, R. S. & Kimura, S., 2009, In : Unknown Journal. 4796419.

Research output: Contribution to journalArticle

4 Citations (Scopus)
Heuristic algorithms
Heuristic algorithm
Sleep
Count
Power Method
VLSI Design
Computer aided design
2008
3 Citations (Scopus)

Issue mechanism for embedded simultaneous multithreading processor

Zang, C., Imai, S., Frank, S. & Kimura, S., 2008, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1092-1100 9 p.

Research output: Contribution to journalArticle

Multithreading
Thread
Pipelines
Clocks
Throughput
1 Citation (Scopus)
Systolic Array
Systolic arrays
Matrix multiplication
Two Dimensions
Hexagon
2006
3 Citations (Scopus)

Bit-length optimization method for high-level synthesis based on non-linear programming technique

Doi, N., Horiyama, T., Nakanishi, M. & Kimura, S., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3427-3434 8 p.

Research output: Contribution to journalArticle

High-level Synthesis
Nonlinear programming
Nonlinear Programming
Optimization Methods
Hardware

Coverage estimation using transition perturbation for symbolic model checking in hardware verification

Xu, X., Kimura, S., Horikawa, K. & Tsuchiya, T., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3451-3457 7 p.

Research output: Contribution to journalArticle

Symbolic Model Checking
Model checking
Coverage
Hardware
Perturbation
2 Citations (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. & 10 others, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.

Research output: Contribution to journalArticle

VLSI Design
Computer aided design
2005
VLSI Design
Computer aided design
2004
Data compression
Data Compression
Glossaries
Slice
Compression
Run Length
Data compression
Data Compression
Reconfiguration
Coding
2003

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

Shi, Y., Zhang, Z., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3056-3062 7 p.

Research output: Contribution to journalArticle

Linear Feedback Shift Register
Seed
Grouping
ROM
Simulated annealing
1 Citation (Scopus)

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Doi, N., Horiyama, T., Nakanishi, M., Kimura, S. & Watanabe, K., 2003 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3184-3191 8 p.

Research output: Contribution to journalArticle

High-level Synthesis
Fractional Parts
Fixed point
Optimization
High level languages
2002

Look up table compaction based on folding of logic functions

Kimura, S., Ishii, A., Horiyama, T., Nakanishi, M., Kajihara, H. & Watanabe, K., 2002 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2701-2707 7 p.

Research output: Contribution to journalArticle

Compaction
Look-up Table
Folding
Logic
Adders
2000
4 Citations (Scopus)
Simplification
Insertion
Cycle
Path
Networks (circuits)

Robust heuristics for multi-level logic simplification considering local circuit structure

Zhu, Q., Matsunaga, Y., Kimura, S. & Watanabe, K., 2000 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2520-2527 8 p.

Research output: Contribution to journalArticle

Simplification
Heuristics
Logic
Data storage equipment
Combinatorial circuits
1999
3 Citations (Scopus)

Exact minimization of free bdds and its application to pass-transistor logic optimization

Takagi, K., Hatakeda, H., Kimura, S. & Watanabe, K., 1999, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2407-2413 7 p.

Research output: Contribution to journalArticle

Transistors
Logic
Logic Synthesis
Boolean functions
Optimization
5 Citations (Scopus)

Hardware synthesis from C programs with estimation of bit length of variables

Ogawa, O., Takagi, K., Itoh, Y., Kimura, S. & Watanabe, K., 1999, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2338-2346 9 p.

Research output: Contribution to journalArticle

Hardware
Synthesis
Compiler
High level languages
Networks (circuits)
1998
2 Citations (Scopus)

Timing verification of sequential logic circuits based on controlled multi-clock path analysis

Nakamura, K., Kimura, S., Takagi, K. & Watanabe, K., 1998, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2515-2520 6 p.

Research output: Contribution to journalArticle

Path Analysis
Sequential circuits
Clocks
Timing
Logic
1993

Preciseness of discrete time verification

Kimura, S., Tsubota, S. & Haneda, H., 1993 Oct, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E76-A, 10, p. 1755-1756 2 p.

Research output: Contribution to journalArticle

Logic circuits
Time delay
Discrete-time
Unit
Delay Time
1987

DESCRIPTION AND VERIFICATION OF INPUT CONSTRAINTS AND INPUT-OUTPUT SPECIFICATIONS OF LOGIC CIRCUITS.

Kimura, S. & Yajima, S., 1987 Feb, In : Systems and Computers in Japan. 18, 2, p. 29-42 14 p.

Research output: Contribution to journalArticle

Input Constraints
Logic circuits
Logic
Specification
Specifications