• 248 Citations
  • 7 h-Index
1980 …2019

Research output per year

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Research Output

2019

A low-power shared cache design with modified PID controller for efficient multicore embedded systems

Zhao, H., Ye, J. & Watanabe, T., 2019 Jan 1, In : Journal of information processing. 27, p. 149-158 10 p.

Research output: Contribution to journalArticle

Open Access
1 Citation (Scopus)

A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA

Zhou, T., Pan, T., Bao, Z. & Watanabe, T., 2019 Jan 2, 2018 5th International Conference on Systems and Informatics, ICSAI 2018. Institute of Electrical and Electronics Engineers Inc., p. 501-506 6 p. 8599330. (2018 5th International Conference on Systems and Informatics, ICSAI 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Filter router: An enhanced router design for efficient stacked shared cache network

Zhao, H., Jia, X. & Watanabe, T., 2019 Jan 1, In : ieice electronics express. 16, 14, 20190358.

Research output: Contribution to journalLetter

Open Access
1 Citation (Scopus)

Wavelength-selective fog-computing network for big-data analytics of Wireless Data

Meyer, M. C., Wang, Y. & Watanabe, T., 2019 May 3, ICEIC 2019 - International Conference on Electronics, Information, and Communication. Institute of Electrical and Electronics Engineers Inc., 8706464. (ICEIC 2019 - International Conference on Electronics, Information, and Communication).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2018

An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips

Dai, J., Jiang, X., Li, R. & Watanabe, T., 2018 Mar 26, Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 29-36 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Design of high-throughput SHA-256 hash function based on FPGA

Binti Suhaili, S. & Watanabe, T., 2018 Mar 9, Proceedings of the 2017 6th International Conference on Electrical Engineering and Informatics: Sustainable Society Through Digital Innovation, ICEEI 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-November. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Efficient simulated annealing-based placement algorithm for Island style FPGAs

Shi, R., Ma, L. & Watanabe, T., 2018 Dec 1, In : International Journal of Machine Learning and Computing. 8, 6, p. 542-548 7 p.

Research output: Contribution to journalArticle

Hybrid path-diversity-dominant output selection method for Network-on-Chip systems

Dai, J., Ma, W., Jiang, X. & Watanabe, T., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 125-126 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs

Dai, J., Li, R., Jiang, X. & Watanabe, T., 2018 May 9, 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, Vol. 2018-March. p. 131-137 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2017

A fast online task placement algorithm on 3D partially reconfigurable devices

Zhou, T., Pan, T. & Watanabe, T., 2017 Dec 19, TENCON 2017 - 2017 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-December. p. 427-432 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip

Dai, J., Jiang, X. & Watanabe, T., 2017 Sep 12, IEEE CITS 2017 - 2017 International Conference on Computer, Information and Telecommunication Systems. Institute of Electrical and Electronics Engineers Inc., p. 229-233 5 p. 8035332

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Behavior-Aware cache hierarchy optimization for low-power multi-core embedded systems

Zhao, H., Luo, X., Zhu, C., Watanabe, T. & Zhu, T., 2017 Jul 30, In : Modern Physics Letters B. 31, 19-21, 1740067.

Research output: Contribution to journalArticle

1 Citation (Scopus)

High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC

Jiang, X., Lei, X., Zeng, L. & Watanabe, T., 2017 May 2, Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, p. 289-295 7 p. 7918330

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

High speed implementation of the keyed-hash message authentication code (HMAC) based on SHA-1 algorithm

Suhaili, S. B. & Watanabe, T., 2017 Nov 1, In : Advanced Science Letters. 23, 11, p. 11096-11100 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

PWSF: Planar-west-South-first routing algorithm for 3D Network-on-Chip

Dai, J., Li, R., Jiang, X. & Watanabe, T., 2017 Dec 19, TENCON 2017 - 2017 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-December. p. 421-426 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016

A fast MER enumeration algorithm for online task placement on reconfigurable FPGAs

Pan, T., Zeng, L., Takashima, Y. & Watanabe, T., 2016 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2412-2424 13 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

An efficient highly adaptive and deadlock-free routing algorithm for 3D network-on-chip

Zengy, L., Pan, T., Jiang, X. & Watanabe, T., 2016 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1334-1344 11 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)

An online task placement algorithm based on MER enumeration for partially reconfigurable device

Pan, T., Zhu, L., Zeng, L., Watanabe, T. & Takashima, Y., 2016 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1345-1354 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

Zeng, L., Pan, T., Jiang, X. & Watanabe, T., 2016 Jan 5, IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-January. 7373036

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A sorting-based micro-bump assignment for 3D ICs

Zhang, R., Pan, T. & Watanabe, T., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 139-140 2 p. 7401697

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Fully adaptive thermal-aware routing for runtime thermal management of 3D network-on-chip

Jiang, X., Lei, X., Zeng, L. & Watanabe, T., 2016, IMECS 2016 - International Multiconference of Engineers and Computer Scientists 2016. Newswood Limited, Vol. 2. p. 659-664 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

High throughput evaluation of SHA-1 implementation using unfolding transformation

Suhaili, S. B. & Watanabe, T., 2016 Mar 1, In : ARPN Journal of Engineering and Applied Sciences. 11, 5, p. 3350-3355 6 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Vertical-mesh-conscious-dynamic routing algorithm for 3D NoCs

Lei, X., Jiang, X., Zeng, L. & Watanabe, T., 2016 Jan 5, IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-January. 7373085

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2015

Adaptive Look Ahead algorithm for 2-D mesh NoC

Menon, A., Zeng, L., Jiang, X. & Watanabe, T., 2015 Jul 10, Souvenir of the 2015 IEEE International Advance Computing Conference, IACC 2015. Institute of Electrical and Electronics Engineers Inc., p. 299-302 4 p. 7154718

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A length matching routing method for disordered pins in PCB design

Zhang, R., Pan, T., Zhu, L. & Watanabe, T., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 402-407 6 p. 7059038

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A performance enhanced dual-switch network-on-chip architecture

Zeng, L., Jiang, X. & Watanabe, T., 2015 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 8, p. 85-94 10 p.

Research output: Contribution to journalArticle

A performance enhanced dual-switch Network-on-Chip architecture

Zeng, L. & Watanabe, T., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 69-74 6 p. 7058983

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Application-specific shared last-level cache optimization for low-power embedded systems

Zhao, H., Ye, J., Su, X. & Watanabe, T., 2015 Aug 6, Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015. Institute of Electrical and Electronics Engineers Inc., 7181994

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A randomized algorithm for the fixed-length routing problem

Pan, T., Zhang, R., Takashima, Y. & Watanabe, T., 2015 Feb 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 711-714 4 p. 7032880. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Improved delay-matching bus routing by using multi-layers

Tian, Y. & Watanabe, T., 2015 May 20, ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc., p. 708-713 6 p. 7111103

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Layer assignment and equal-length routing for disordered pins in PCB Design

Zhang, R., Pan, T., Zhu, L. & Watanabe, T., 2015 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 8, p. 75-84 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Sorting-based I/O connection assignment and non-Manhattan RDL routing for flip-chip designs

Zhang, R. & Watanabe, T., 2015 Dec 1, In : IEEJ Transactions on Electronics, Information and Systems. 135, 12, p. 1535-1544 10 p.

Research output: Contribution to journalArticle

2014

A sophisticated routing algorithm in 3D NoC with fixed TSVs for low energy and latency

Jiang, X., Zeng, L. & Watanabe, T., 2014, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 101-109 9 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Efficient delay-matching bus routing by using multi-layers

Tian, Y., Zhang, R. & Watanabe, T., 2014 Jan 1, 2014 International Conference on Electronics Packaging, ICEP 2014. IEEE Computer Society, p. 728-731 4 p. 6826776. (2014 International Conference on Electronics Packaging, ICEP 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2013

Adaptive router with predictor using congestion degree for 3D Network-on-Chip

Zeng, L., Jiang, X. & Watanabe, T., 2013 Jan 1, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 46-49 4 p. 6863982. (ISOCC 2013 - 2013 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An efficient algorithm for 3d NOC architecture optimization

Jiang, X., Zhang, R. & Watanabe, T., 2013 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 6, p. 34-41 8 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A novel fully adaptive fault-tolerant routing algorithm for 3D Network-on-Chip

Jiang, X. & Watanabe, T., 2013 Dec 1, 2013 IEEE International Conference of IEEE Region 10, IEEE TENCON 2013 - Conference Proceedings. 6718932. (IEEE Region 10 Annual International Conference, Proceedings/TENCON).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A parallel routing method for fixed pins using virtual boundary

Zhang, R. & Watanabe, T., 2013 Sep 16, IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings. p. 99-103 5 p. 6584425. (IEEE 2013 Tencon - Spring, TENCONSpring 2013 - Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A sorting-based IO connection assignment for flip-chip designs

Zhang, R., Wei, X. & Watanabe, T., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811927. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Flexible L1 cache optimization for a low power embedded system

Zhao, H., Yin, S., Sun, Y. & Watanabe, T., 2013 Jan 1, Proceedings - 2013 International Conference on Mechatronic Sciences, Electric Engineering and Computer, MEC 2013. Institute of Electrical and Electronics Engineers Inc., p. 2433-2437 5 p. 6885444. (Proceedings - 2013 International Conference on Mechatronic Sciences, Electric Engineering and Computer, MEC 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors

Zhao, H., Ye, J., Sun, Y. & Watanabe, T., 2013 Jan 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811990. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2012

A behavior-based adaptive access-mode for low-power set-associative caches in embedded systems

Ye, J., Ding, H., Hu, Y. & Watanabe, T., 2012 Jan 1, In : Journal of information processing. 20, 1, p. 26-36 11 p.

Research output: Contribution to journalArticle

Open Access
1 Citation (Scopus)

Region-oriented placement algorithm for coarse-grained power-gating FPGA architecture

Li, C., Dong, Y. & Watanabe, T., 2012 Feb, In : IEICE Transactions on Information and Systems. E95-D, 2, p. 314-323 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Region oriented routing FPGA architecture for dynamic power gating

Li, C., Dong, Y. & Watanabe, T., 2012 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 12, p. 2199-2207 9 p.

Research output: Contribution to journalArticle

2011

A behavior-based reconfigurable cache for the low-power embedded processor

Ye, J., Jin, J. & Watanabe, T., 2011 Dec 1, Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. p. 1-5 5 p. 6157107. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A high performance digital neural processor design by Network on Chip architecture

Yiping, D., Ce, L., Hui, L. & Takahiro, W., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 243-246 4 p. 5783621. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An adaptive various-width data cache for low power design

Ye, J., Wan, Y. & Watanabe, T., 2011 Aug, In : IEICE Transactions on Information and Systems. E94-D, 8, p. 1539-1546 8 p.

Research output: Contribution to journalArticle

Analysis before starting an access: A new power-efficient instruction fetch mechanism

Ye, J., Hu, Y., Ding, H. & Watanabe, T., 2011 Jul, In : IEICE Transactions on Information and Systems. E94-D, 7, p. 1398-1408 11 p.

Research output: Contribution to journalArticle