0.15 μm CMOS process for high performance and high reliability

S. Shimizu, T. Kuroi, M. Kobayashi, T. Yamaguchi, T. Fujino, H. Maeda, T. Tsutsumi, Y. Hirose, S. Kusunoki, Masahide Inuishi, N. Tsubouchi

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

Original languageEnglish
Pages (from-to)67-70
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1994
Externally publishedYes

Fingerprint

implantation
CMOS
Hot carriers
Masks
Time delay
Capacitance
Nitrogen
Degradation
Electrodes
Oxides
Electric potential
time lag
masks
capacitance
oscillators
degradation
nitrogen
electrodes
oxides
propagation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Shimizu, S., Kuroi, T., Kobayashi, M., Yamaguchi, T., Fujino, T., Maeda, H., ... Tsubouchi, N. (1994). 0.15 μm CMOS process for high performance and high reliability. Unknown Journal, 67-70.

0.15 μm CMOS process for high performance and high reliability. / Shimizu, S.; Kuroi, T.; Kobayashi, M.; Yamaguchi, T.; Fujino, T.; Maeda, H.; Tsutsumi, T.; Hirose, Y.; Kusunoki, S.; Inuishi, Masahide; Tsubouchi, N.

In: Unknown Journal, 1994, p. 67-70.

Research output: Contribution to journalArticle

Shimizu, S, Kuroi, T, Kobayashi, M, Yamaguchi, T, Fujino, T, Maeda, H, Tsutsumi, T, Hirose, Y, Kusunoki, S, Inuishi, M & Tsubouchi, N 1994, '0.15 μm CMOS process for high performance and high reliability', Unknown Journal, pp. 67-70.
Shimizu S, Kuroi T, Kobayashi M, Yamaguchi T, Fujino T, Maeda H et al. 0.15 μm CMOS process for high performance and high reliability. Unknown Journal. 1994;67-70.
Shimizu, S. ; Kuroi, T. ; Kobayashi, M. ; Yamaguchi, T. ; Fujino, T. ; Maeda, H. ; Tsutsumi, T. ; Hirose, Y. ; Kusunoki, S. ; Inuishi, Masahide ; Tsubouchi, N. / 0.15 μm CMOS process for high performance and high reliability. In: Unknown Journal. 1994 ; pp. 67-70.
@article{d2ee8d1ddd7d46dabca08beb0bc84525,
title = "0.15 μm CMOS process for high performance and high reliability",
abstract = "We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.",
author = "S. Shimizu and T. Kuroi and M. Kobayashi and T. Yamaguchi and T. Fujino and H. Maeda and T. Tsutsumi and Y. Hirose and S. Kusunoki and Masahide Inuishi and N. Tsubouchi",
year = "1994",
language = "English",
pages = "67--70",
journal = "Nuclear Physics A",
issn = "0375-9474",
publisher = "Elsevier",

}

TY - JOUR

T1 - 0.15 μm CMOS process for high performance and high reliability

AU - Shimizu, S.

AU - Kuroi, T.

AU - Kobayashi, M.

AU - Yamaguchi, T.

AU - Fujino, T.

AU - Maeda, H.

AU - Tsutsumi, T.

AU - Hirose, Y.

AU - Kusunoki, S.

AU - Inuishi, Masahide

AU - Tsubouchi, N.

PY - 1994

Y1 - 1994

N2 - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

AB - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

UR - http://www.scopus.com/inward/record.url?scp=0028736933&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028736933&partnerID=8YFLogxK

M3 - Article

SP - 67

EP - 70

JO - Nuclear Physics A

JF - Nuclear Physics A

SN - 0375-9474

ER -