0.15 μm CMOS process for high performance and high reliability

S. Shimizu; T. Kuroi; M. Kobayashi; T. Yamaguchi; T. Fujino; H. Maeda; T. Tsutsumi; Y. Hirose; S. Kusunoki; M. Inuishi; N. Tsubouchi

0.15 μm CMOS process for high performance and high reliability

S. Shimizu^*, T. Kuroi, M. Kobayashi, T. Yamaguchi, T. Fujino, H. Maeda, T. Tsutsumi, Y. Hirose, S. Kusunoki, M. Inuishi, N. Tsubouchi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

12 Citations (Scopus)

Abstract

We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi₂/Si interface using Si⁺ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

Original language	English
Pages (from-to)	67-70
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1994 Dec 1
Externally published	Yes
Event	Proceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 1994 Dec 11 → 1994 Dec 14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

0.15 μm CMOS process for high performance and high reliability. / Shimizu, S.; Kuroi, T.; Kobayashi, M.; Yamaguchi, T.; Fujino, T.; Maeda, H.; Tsutsumi, T.; Hirose, Y.; Kusunoki, S.; Inuishi, M.; Tsubouchi, N.

In: Technical Digest - International Electron Devices Meeting, 01.12.1994, p. 67-70.

Research output: Contribution to journal › Conference article › peer-review

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abstract = "We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.",

author = "S. Shimizu and T. Kuroi and M. Kobayashi and T. Yamaguchi and T. Fujino and H. Maeda and T. Tsutsumi and Y. Hirose and S. Kusunoki and M. Inuishi and N. Tsubouchi",

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T1 - 0.15 μm CMOS process for high performance and high reliability

AU - Shimizu, S.

AU - Kuroi, T.

AU - Kobayashi, M.

AU - Yamaguchi, T.

AU - Fujino, T.

AU - Maeda, H.

AU - Tsutsumi, T.

AU - Hirose, Y.

AU - Kusunoki, S.

AU - Inuishi, M.

AU - Tsubouchi, N.

PY - 1994/12/1

Y1 - 1994/12/1

N2 - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

AB - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

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SP - 67

EP - 70

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - Proceedings of the 1994 IEEE International Electron Devices Meeting

Y2 - 11 December 1994 through 14 December 1994

ER -

0.15 μm CMOS process for high performance and high reliability

Abstract

ASJC Scopus subject areas

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