0.15 μm CMOS process for high performance and high reliability

S. Shimizu, T. Kuroi, M. Kobayashi, T. Yamaguchi, T. Fujino, H. Maeda, T. Tsutsumi, Y. Hirose, S. Kusunoki, Masahide Inuishi, N. Tsubouchi

Research output: Contribution to journalArticle

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Abstract

We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

Original languageEnglish
Pages (from-to)67-70
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1994
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Shimizu, S., Kuroi, T., Kobayashi, M., Yamaguchi, T., Fujino, T., Maeda, H., Tsutsumi, T., Hirose, Y., Kusunoki, S., Inuishi, M., & Tsubouchi, N. (1994). 0.15 μm CMOS process for high performance and high reliability. Unknown Journal, 67-70.