0.15 μm CMOS process for high performance and high reliability

S. Shimizu*, T. Kuroi, M. Kobayashi, T. Yamaguchi, T. Fujino, H. Maeda, T. Tsutsumi, Y. Hirose, S. Kusunoki, M. Inuishi, N. Tsubouchi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

12 Citations (Scopus)

Abstract

We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

Original languageEnglish
Pages (from-to)67-70
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1994 Dec 1
Externally publishedYes
EventProceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1994 Dec 111994 Dec 14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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