Abstract
We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.
| Original language | English |
|---|---|
| Pages (from-to) | 67-70 |
| Number of pages | 4 |
| Journal | Unknown Journal |
| Publication status | Published - 1994 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
0.15 μm CMOS process for high performance and high reliability. / Shimizu, S.; Kuroi, T.; Kobayashi, M.; Yamaguchi, T.; Fujino, T.; Maeda, H.; Tsutsumi, T.; Hirose, Y.; Kusunoki, S.; Inuishi, Masahide; Tsubouchi, N.
In: Unknown Journal, 1994, p. 67-70.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - 0.15 μm CMOS process for high performance and high reliability
AU - Shimizu, S.
AU - Kuroi, T.
AU - Kobayashi, M.
AU - Yamaguchi, T.
AU - Fujino, T.
AU - Maeda, H.
AU - Tsutsumi, T.
AU - Hirose, Y.
AU - Kusunoki, S.
AU - Inuishi, Masahide
AU - Tsubouchi, N.
PY - 1994
Y1 - 1994
N2 - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.
AB - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.
UR - http://www.scopus.com/inward/record.url?scp=0028736933&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028736933&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0028736933
SP - 67
EP - 70
JO - Nuclear Physics A
JF - Nuclear Physics A
SN - 0375-9474
ER -