0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.

Original languageEnglish
Pages (from-to)1680-1689
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume35
Issue number11
DOIs
Publication statusPublished - 2000 Nov
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kuge, S., Kato, T., Furutani, K., Kikuda, S., Mitsui, K., Hamamoto, T., Setogawa, J., Hamade, K., Komiya, Y., Kawasaki, S., Kono, T., Amano, T., Kubo, T., Haraguchi, M., Nakaoka, Y., Akiyama, M., Konishi, Y., Ozaki, H., & Yoshihara, T. (2000). 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE Journal of Solid-State Circuits, 35(11), 1680-1689. https://doi.org/10.1109/4.881215