0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies.

Original languageEnglish
Title of host publicationESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages354-357
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
Duration: 2010 Sep 142010 Sep 16

Other

Other36th European Solid State Circuits Conference, ESSCIRC 2010
CountrySpain
CitySevilla
Period10/9/1410/9/16

Fingerprint

Static random access storage
Transistors
Electric potential
Leakage currents
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Suzuki, T., Moriwaki, S., Kawasumi, A., Miyano, S., & Shinohara, H. (2010). 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. In ESSCIRC 2010 - 36th European Solid State Circuits Conference (pp. 354-357). [5619716] https://doi.org/10.1109/ESSCIRC.2010.5619716

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. / Suzuki, Toshikazu; Moriwaki, Shinichi; Kawasumi, Atsushi; Miyano, Shinji; Shinohara, Hirofumi.

ESSCIRC 2010 - 36th European Solid State Circuits Conference. 2010. p. 354-357 5619716.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, T, Moriwaki, S, Kawasumi, A, Miyano, S & Shinohara, H 2010, 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. in ESSCIRC 2010 - 36th European Solid State Circuits Conference., 5619716, pp. 354-357, 36th European Solid State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, 10/9/14. https://doi.org/10.1109/ESSCIRC.2010.5619716
Suzuki T, Moriwaki S, Kawasumi A, Miyano S, Shinohara H. 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. In ESSCIRC 2010 - 36th European Solid State Circuits Conference. 2010. p. 354-357. 5619716 https://doi.org/10.1109/ESSCIRC.2010.5619716
Suzuki, Toshikazu ; Moriwaki, Shinichi ; Kawasumi, Atsushi ; Miyano, Shinji ; Shinohara, Hirofumi. / 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC 2010 - 36th European Solid State Circuits Conference. 2010. pp. 354-357
@inproceedings{c9d7056ed4c744aaacde6f2e2557916e,
title = "0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme",
abstract = "A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52{\%} and 54{\%}, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64{\%} compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies.",
author = "Toshikazu Suzuki and Shinichi Moriwaki and Atsushi Kawasumi and Shinji Miyano and Hirofumi Shinohara",
year = "2010",
doi = "10.1109/ESSCIRC.2010.5619716",
language = "English",
isbn = "9781424466641",
pages = "354--357",
booktitle = "ESSCIRC 2010 - 36th European Solid State Circuits Conference",

}

TY - GEN

T1 - 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

AU - Suzuki, Toshikazu

AU - Moriwaki, Shinichi

AU - Kawasumi, Atsushi

AU - Miyano, Shinji

AU - Shinohara, Hirofumi

PY - 2010

Y1 - 2010

N2 - A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies.

AB - A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies.

UR - http://www.scopus.com/inward/record.url?scp=78650375733&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650375733&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2010.5619716

DO - 10.1109/ESSCIRC.2010.5619716

M3 - Conference contribution

SN - 9781424466641

SP - 354

EP - 357

BT - ESSCIRC 2010 - 36th European Solid State Circuits Conference

ER -