0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies.

Original languageEnglish
Title of host publicationESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages354-357
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
Duration: 2010 Sep 142010 Sep 16

Other

Other36th European Solid State Circuits Conference, ESSCIRC 2010
CountrySpain
CitySevilla
Period10/9/1410/9/16

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Suzuki, T., Moriwaki, S., Kawasumi, A., Miyano, S., & Shinohara, H. (2010). 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. In ESSCIRC 2010 - 36th European Solid State Circuits Conference (pp. 354-357). [5619716] https://doi.org/10.1109/ESSCIRC.2010.5619716