0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura; A. Muramatsu; H. Takeno; S. Hattori; D. Ogawa; M. Nasu; K. Hirairi; S. Kumashiro; S. Moriwaki; Y. Yamamoto; S. Miyano; Y. Hiraku; I. Hayashi; K. Yoshioka; A. Shikata; H. Ishikuro; M. Ahn; Y. Okuma; X. Zhang; Y. Ryu; K. Ishida; M. Takamiya; T. Kuroda; H. Shinohara; T. Sakurai

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. RyuK. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

Original language	English
Title of host publication	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Pages	C36-C37
Publication status	Published - 2013 Sep 17
Externally published	Yes
Event	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 2013 Jun 12 → 2013 Jun 14

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2013 Symposium on VLSI Circuits, VLSIC 2013
Country/Territory	Japan
City	Kyoto
Period	13/6/12 → 13/6/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., ... Sakurai, T. (2013). 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C36-C37). [6578745] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. / Nomura, M.; Muramatsu, A.; Takeno, H.; Hattori, S.; Ogawa, D.; Nasu, M.; Hirairi, K.; Kumashiro, S.; Moriwaki, S.; Yamamoto, Y.; Miyano, S.; Hiraku, Y.; Hayashi, I.; Yoshioka, K.; Shikata, A.; Ishikuro, H.; Ahn, M.; Okuma, Y.; Zhang, X.; Ryu, Y.; Ishida, K.; Takamiya, M.; Kuroda, T.; Shinohara, H.; Sakurai, T.

2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C36-C37 6578745 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nomura, M, Muramatsu, A, Takeno, H, Hattori, S, Ogawa, D, Nasu, M, Hirairi, K, Kumashiro, S, Moriwaki, S, Yamamoto, Y, Miyano, S, Hiraku, Y, Hayashi, I, Yoshioka, K, Shikata, A, Ishikuro, H, Ahn, M, Okuma, Y, Zhang, X, Ryu, Y, Ishida, K, Takamiya, M, Kuroda, T, Shinohara, H & Sakurai, T 2013, 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578745, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. C36-C37, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.

Nomura M, Muramatsu A, Takeno H, Hattori S, Ogawa D, Nasu M et al. 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C36-C37. 6578745. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Nomura, M. ; Muramatsu, A. ; Takeno, H. ; Hattori, S. ; Ogawa, D. ; Nasu, M. ; Hirairi, K. ; Kumashiro, S. ; Moriwaki, S. ; Yamamoto, Y. ; Miyano, S. ; Hiraku, Y. ; Hayashi, I. ; Yoshioka, K. ; Shikata, A. ; Ishikuro, H. ; Ahn, M. ; Okuma, Y. ; Zhang, X. ; Ryu, Y. ; Ishida, K. ; Takamiya, M. ; Kuroda, T. ; Shinohara, H. ; Sakurai, T. / 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. pp. C36-C37 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{707cd5940a064bff8b8066ad9df23955,

title = "0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS",

abstract = "A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.",

author = "M. Nomura and A. Muramatsu and H. Takeno and S. Hattori and D. Ogawa and M. Nasu and K. Hirairi and S. Kumashiro and S. Moriwaki and Y. Yamamoto and S. Miyano and Y. Hiraku and I. Hayashi and K. Yoshioka and A. Shikata and H. Ishikuro and M. Ahn and Y. Okuma and X. Zhang and Y. Ryu and K. Ishida and M. Takamiya and T. Kuroda and H. Shinohara and T. Sakurai",

year = "2013",

month = sep,

day = "17",

language = "English",

isbn = "9784863483484",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "C36--C37",

booktitle = "2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers",

note = "2013 Symposium on VLSI Circuits, VLSIC 2013 ; Conference date: 12-06-2013 Through 14-06-2013",

}

TY - GEN

T1 - 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

AU - Nomura, M.

AU - Muramatsu, A.

AU - Takeno, H.

AU - Hattori, S.

AU - Ogawa, D.

AU - Nasu, M.

AU - Hirairi, K.

AU - Kumashiro, S.

AU - Moriwaki, S.

AU - Yamamoto, Y.

AU - Miyano, S.

AU - Hiraku, Y.

AU - Hayashi, I.

AU - Yoshioka, K.

AU - Shikata, A.

AU - Ishikuro, H.

AU - Ahn, M.

AU - Okuma, Y.

AU - Zhang, X.

AU - Ryu, Y.

AU - Ishida, K.

AU - Takamiya, M.

AU - Kuroda, T.

AU - Shinohara, H.

AU - Sakurai, T.

PY - 2013/9/17

Y1 - 2013/9/17

N2 - A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

AB - A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

UR - http://www.scopus.com/inward/record.url?scp=84883767387&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883767387&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84883767387

SN - 9784863483484

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C36-C37

BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers

T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013

Y2 - 12 June 2013 through 14 June 2013

ER -

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Abstract

Publication series

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this