0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. RyuK. Ishida, M. Takamiya, T. Kuroda, Hirofumi Shinohara, T. Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publication statusPublished - 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period13/6/1213/6/14

Fingerprint

Program processors
Clocks
Electric potential
Logic design
Energy efficiency
Buffers
Processing
Dynamic frequency scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., ... Sakurai, T. (2013). 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers [6578745]

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. / Nomura, M.; Muramatsu, A.; Takeno, H.; Hattori, S.; Ogawa, D.; Nasu, M.; Hirairi, K.; Kumashiro, S.; Moriwaki, S.; Yamamoto, Y.; Miyano, S.; Hiraku, Y.; Hayashi, I.; Yoshioka, K.; Shikata, A.; Ishikuro, H.; Ahn, M.; Okuma, Y.; Zhang, X.; Ryu, Y.; Ishida, K.; Takamiya, M.; Kuroda, T.; Shinohara, Hirofumi; Sakurai, T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578745.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nomura, M, Muramatsu, A, Takeno, H, Hattori, S, Ogawa, D, Nasu, M, Hirairi, K, Kumashiro, S, Moriwaki, S, Yamamoto, Y, Miyano, S, Hiraku, Y, Hayashi, I, Yoshioka, K, Shikata, A, Ishikuro, H, Ahn, M, Okuma, Y, Zhang, X, Ryu, Y, Ishida, K, Takamiya, M, Kuroda, T, Shinohara, H & Sakurai, T 2013, 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 6578745, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.
Nomura M, Muramatsu A, Takeno H, Hattori S, Ogawa D, Nasu M et al. 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578745
Nomura, M. ; Muramatsu, A. ; Takeno, H. ; Hattori, S. ; Ogawa, D. ; Nasu, M. ; Hirairi, K. ; Kumashiro, S. ; Moriwaki, S. ; Yamamoto, Y. ; Miyano, S. ; Hiraku, Y. ; Hayashi, I. ; Yoshioka, K. ; Shikata, A. ; Ishikuro, H. ; Ahn, M. ; Okuma, Y. ; Zhang, X. ; Ryu, Y. ; Ishida, K. ; Takamiya, M. ; Kuroda, T. ; Shinohara, Hirofumi ; Sakurai, T. / 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013.
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abstract = "A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 {\%}, 13{\%}, and 6{\%}, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33{\%}.",
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AU - Takeno, H.

AU - Hattori, S.

AU - Ogawa, D.

AU - Nasu, M.

AU - Hirairi, K.

AU - Kumashiro, S.

AU - Moriwaki, S.

AU - Yamamoto, Y.

AU - Miyano, S.

AU - Hiraku, Y.

AU - Hayashi, I.

AU - Yoshioka, K.

AU - Shikata, A.

AU - Ishikuro, H.

AU - Ahn, M.

AU - Okuma, Y.

AU - Zhang, X.

AU - Ryu, Y.

AU - Ishida, K.

AU - Takamiya, M.

AU - Kuroda, T.

AU - Shinohara, Hirofumi

AU - Sakurai, T.

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