Abstract
A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.
| Original language | English |
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| Title of host publication | 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers |
| Pages | C36-C37 |
| Publication status | Published - 2013 Sep 17 |
| Event | 2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 2013 Jun 12 → 2013 Jun 14 |
Publication series
| Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Other
| Other | 2013 Symposium on VLSI Circuits, VLSIC 2013 |
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| Country | Japan |
| City | Kyoto |
| Period | 13/6/12 → 13/6/14 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., ... Sakurai, T. (2013). 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C36-C37). [6578745] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).