Abstract
A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.
| Original language | English |
|---|---|
| Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| Publication status | Published - 2013 |
| Externally published | Yes |
| Event | 2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 2013 Jun 12 → 2013 Jun 14 |
Other
| Other | 2013 Symposium on VLSI Circuits, VLSIC 2013 |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 13/6/12 → 13/6/14 |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. / Nomura, M.; Muramatsu, A.; Takeno, H.; Hattori, S.; Ogawa, D.; Nasu, M.; Hirairi, K.; Kumashiro, S.; Moriwaki, S.; Yamamoto, Y.; Miyano, S.; Hiraku, Y.; Hayashi, I.; Yoshioka, K.; Shikata, A.; Ishikuro, H.; Ahn, M.; Okuma, Y.; Zhang, X.; Ryu, Y.; Ishida, K.; Takamiya, M.; Kuroda, T.; Shinohara, Hirofumi; Sakurai, T.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578745.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS
AU - Nomura, M.
AU - Muramatsu, A.
AU - Takeno, H.
AU - Hattori, S.
AU - Ogawa, D.
AU - Nasu, M.
AU - Hirairi, K.
AU - Kumashiro, S.
AU - Moriwaki, S.
AU - Yamamoto, Y.
AU - Miyano, S.
AU - Hiraku, Y.
AU - Hayashi, I.
AU - Yoshioka, K.
AU - Shikata, A.
AU - Ishikuro, H.
AU - Ahn, M.
AU - Okuma, Y.
AU - Zhang, X.
AU - Ryu, Y.
AU - Ishida, K.
AU - Takamiya, M.
AU - Kuroda, T.
AU - Shinohara, Hirofumi
AU - Sakurai, T.
PY - 2013
Y1 - 2013
N2 - A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.
AB - A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.
UR - http://www.scopus.com/inward/record.url?scp=84883767387&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883767387&partnerID=8YFLogxK
M3 - Conference contribution
SN - 9784863483484
BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ER -