0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. RyuK. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
PagesC36-C37
Publication statusPublished - 2013 Sep 9
Externally publishedYes
Event2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan
Duration: 2013 Jun 112013 Jun 13

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2013 Symposium on VLSI Technology, VLSIT 2013
CountryJapan
CityKyoto
Period13/6/1113/6/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., ... Sakurai, T. (2013). 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers (pp. C36-C37). [6576619] (Digest of Technical Papers - Symposium on VLSI Technology).