Abstract
In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively.
| Original language | English |
|---|---|
| Title of host publication | ISPD 2017 - Proceedings of the 2017 ACM International Symposium on Physical Design |
| Publisher | Association for Computing Machinery |
| Pages | 121-122 |
| Number of pages | 2 |
| Volume | Part F127197 |
| ISBN (Electronic) | 9781450346962 |
| DOIs | |
| Publication status | Published - 2017 Mar 19 |
| Event | 2017 ACM International Symposium on Physical Design, ISPD 2017 - Portland, United States Duration: 2017 Mar 19 → 2017 Mar 22 |
Other
| Other | 2017 ACM International Symposium on Physical Design, ISPD 2017 |
|---|---|
| Country | United States |
| City | Portland |
| Period | 17/3/19 → 17/3/22 |
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Keywords
- Low power
- Memory bandwidth
- UHDTV
- Video coding
- VLSI
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
100x evolution of video codec chips. / Zhou, Jinjia; Zhou, Dajiang; Goto, Satoshi.
ISPD 2017 - Proceedings of the 2017 ACM International Symposium on Physical Design. Vol. Part F127197 Association for Computing Machinery, 2017. p. 121-122.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 100x evolution of video codec chips
AU - Zhou, Jinjia
AU - Zhou, Dajiang
AU - Goto, Satoshi
PY - 2017/3/19
Y1 - 2017/3/19
N2 - In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively.
AB - In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively.
KW - Low power
KW - Memory bandwidth
KW - UHDTV
KW - Video coding
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=85022056945&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85022056945&partnerID=8YFLogxK
U2 - 10.1145/3036669.3038252
DO - 10.1145/3036669.3038252
M3 - Conference contribution
AN - SCOPUS:85022056945
VL - Part F127197
SP - 121
EP - 122
BT - ISPD 2017 - Proceedings of the 2017 ACM International Symposium on Physical Design
PB - Association for Computing Machinery
ER -