Abstract
In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively.
Original language | English |
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Title of host publication | ISPD 2017 - Proceedings of the 2017 ACM International Symposium on Physical Design |
Publisher | Association for Computing Machinery |
Pages | 121-122 |
Number of pages | 2 |
Volume | Part F127197 |
ISBN (Electronic) | 9781450346962 |
DOIs | |
Publication status | Published - 2017 Mar 19 |
Event | 2017 ACM International Symposium on Physical Design, ISPD 2017 - Portland, United States Duration: 2017 Mar 19 → 2017 Mar 22 |
Other
Other | 2017 ACM International Symposium on Physical Design, ISPD 2017 |
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Country/Territory | United States |
City | Portland |
Period | 17/3/19 → 17/3/22 |
Keywords
- Low power
- Memory bandwidth
- UHDTV
- Video coding
- VLSI
ASJC Scopus subject areas
- Electrical and Electronic Engineering