1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit

H. Suzuki, H. Takata, Hirofumi Shinohara, E. Teraoka, M. Matsuo, T. Yoshida, H. Sato, N. Honda, N. Masui, T. Shimizu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages152-153
Number of pages2
Publication statusPublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period06/6/1506/6/17

Fingerprint

Adders
Networks (circuits)
Clocks

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suzuki, H., Takata, H., Shinohara, H., Teraoka, E., Matsuo, M., Yoshida, T., ... Shimizu, T. (2006). 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 152-153). [1705355]

1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. / Suzuki, H.; Takata, H.; Shinohara, Hirofumi; Teraoka, E.; Matsuo, M.; Yoshida, T.; Sato, H.; Honda, N.; Masui, N.; Shimizu, T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 152-153 1705355.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, H, Takata, H, Shinohara, H, Teraoka, E, Matsuo, M, Yoshida, T, Sato, H, Honda, N, Masui, N & Shimizu, T 2006, 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 1705355, pp. 152-153, 2006 Symposium on VLSI Circuits, VLSIC, Honolulu, HI, United States, 06/6/15.
Suzuki H, Takata H, Shinohara H, Teraoka E, Matsuo M, Yoshida T et al. 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 152-153. 1705355
Suzuki, H. ; Takata, H. ; Shinohara, Hirofumi ; Teraoka, E. ; Matsuo, M. ; Yoshida, T. ; Sato, H. ; Honda, N. ; Masui, N. ; Shimizu, T. / 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. pp. 152-153
@inproceedings{31eec34b848b45c7b9a7a532355407b5,
title = "1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit",
abstract = "1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8{\%}. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.",
author = "H. Suzuki and H. Takata and Hirofumi Shinohara and E. Teraoka and M. Matsuo and T. Yoshida and H. Sato and N. Honda and N. Masui and T. Shimizu",
year = "2006",
language = "English",
isbn = "1424400066",
pages = "152--153",
booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

}

TY - GEN

T1 - 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit

AU - Suzuki, H.

AU - Takata, H.

AU - Shinohara, Hirofumi

AU - Teraoka, E.

AU - Matsuo, M.

AU - Yoshida, T.

AU - Sato, H.

AU - Honda, N.

AU - Masui, N.

AU - Shimizu, T.

PY - 2006

Y1 - 2006

N2 - 1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.

AB - 1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.

UR - http://www.scopus.com/inward/record.url?scp=39749184810&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39749184810&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:39749184810

SN - 1424400066

SN - 9781424400065

SP - 152

EP - 153

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

ER -