Abstract
1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.
| Original language | English |
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| Title of host publication | 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers |
| Pages | 152-153 |
| Number of pages | 2 |
| Publication status | Published - 2006 Dec 1 |
| Event | 2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: 2006 Jun 15 → 2006 Jun 17 |
Publication series
| Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Other
| Other | 2006 Symposium on VLSI Circuits, VLSIC |
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| Country | United States |
| City | Honolulu, HI |
| Period | 06/6/15 → 06/6/17 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Suzuki, H., Takata, H., Shinohara, H., Teraoka, E., Matsuo, M., Yoshida, T., Sato, H., Honda, N., Masui, N., & Shimizu, T. (2006). 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. In 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 152-153). [1705355] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).