Abstract
1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.
| Original language | English |
|---|---|
| Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| Pages | 152-153 |
| Number of pages | 2 |
| Publication status | Published - 2006 |
| Externally published | Yes |
| Event | 2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: 2006 Jun 15 → 2006 Jun 17 |
Other
| Other | 2006 Symposium on VLSI Circuits, VLSIC |
|---|---|
| Country | United States |
| City | Honolulu, HI |
| Period | 06/6/15 → 06/6/17 |
Fingerprint
ASJC Scopus subject areas
- Engineering(all)
Cite this
1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. / Suzuki, H.; Takata, H.; Shinohara, Hirofumi; Teraoka, E.; Matsuo, M.; Yoshida, T.; Sato, H.; Honda, N.; Masui, N.; Shimizu, T.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 152-153 1705355.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit
AU - Suzuki, H.
AU - Takata, H.
AU - Shinohara, Hirofumi
AU - Teraoka, E.
AU - Matsuo, M.
AU - Yoshida, T.
AU - Sato, H.
AU - Honda, N.
AU - Masui, N.
AU - Shimizu, T.
PY - 2006
Y1 - 2006
N2 - 1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.
AB - 1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.
UR - http://www.scopus.com/inward/record.url?scp=39749184810&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=39749184810&partnerID=8YFLogxK
M3 - Conference contribution
SN - 1424400066
SN - 9781424400065
SP - 152
EP - 153
BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ER -