12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.

Original languageEnglish
Title of host publicationEuropean Solid-State Circuits Conference
Pages191-194
Number of pages4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
Duration: 2011 Sep 122011 Sep 16

Other

Other37th European Solid-State Circuits Conference, ESSCIRC 2011
CountryFinland
CityHelsinki
Period11/9/1211/9/16

Fingerprint

Logic circuits
Voltage control
Clocks
Electric potential
Flip flop circuits
Cryptography

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Muramatsu, A., Yasufuku, T., Nomura, M., Takamiya, M., Shinohara, H., & Sakurai, T. (2011). 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. In European Solid-State Circuits Conference (pp. 191-194). [6044897] https://doi.org/10.1109/ESSCIRC.2011.6044897

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. / Muramatsu, Atsushi; Yasufuku, Tadashi; Nomura, Masahiro; Takamiya, Makoto; Shinohara, Hirofumi; Sakurai, Takayasu.

European Solid-State Circuits Conference. 2011. p. 191-194 6044897.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Muramatsu, A, Yasufuku, T, Nomura, M, Takamiya, M, Shinohara, H & Sakurai, T 2011, 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. in European Solid-State Circuits Conference., 6044897, pp. 191-194, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 11/9/12. https://doi.org/10.1109/ESSCIRC.2011.6044897
Muramatsu A, Yasufuku T, Nomura M, Takamiya M, Shinohara H, Sakurai T. 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. In European Solid-State Circuits Conference. 2011. p. 191-194. 6044897 https://doi.org/10.1109/ESSCIRC.2011.6044897
Muramatsu, Atsushi ; Yasufuku, Tadashi ; Nomura, Masahiro ; Takamiya, Makoto ; Shinohara, Hirofumi ; Sakurai, Takayasu. / 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. European Solid-State Circuits Conference. 2011. pp. 191-194
@inproceedings{9e73854609c041498c700d05dbcf871c,
title = "12{\%} Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains",
abstract = "Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12{\%} at 1-MHz clock in the measurement.",
author = "Atsushi Muramatsu and Tadashi Yasufuku and Masahiro Nomura and Makoto Takamiya and Hirofumi Shinohara and Takayasu Sakurai",
year = "2011",
doi = "10.1109/ESSCIRC.2011.6044897",
language = "English",
isbn = "9781457707018",
pages = "191--194",
booktitle = "European Solid-State Circuits Conference",

}

TY - GEN

T1 - 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

AU - Muramatsu, Atsushi

AU - Yasufuku, Tadashi

AU - Nomura, Masahiro

AU - Takamiya, Makoto

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2011

Y1 - 2011

N2 - Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.

AB - Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.

UR - http://www.scopus.com/inward/record.url?scp=82955194877&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=82955194877&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2011.6044897

DO - 10.1109/ESSCIRC.2011.6044897

M3 - Conference contribution

AN - SCOPUS:82955194877

SN - 9781457707018

SP - 191

EP - 194

BT - European Solid-State Circuits Conference

ER -