1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology

Uroschanit Yodprasit, Kosuke Katayama, Ryuichi Fujimoto, Mizuki Motoyoshi, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.

Original languageEnglish
Title of host publication2013 IEEE International Semiconductor Conference Dresden - Grenoble
Subtitle of host publicationTechnology, Design, Packaging, Simulation and Test, ISCDG 2013
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 - Dresden, Germany
Duration: 2013 Sep 262013 Sep 27

Other

Other2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013
CountryGermany
CityDresden
Period13/9/2613/9/27

Fingerprint

Power amplifiers
Wave transmission
Frequency bands
Electric lines
Bandwidth
Communication
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yodprasit, U., Katayama, K., Fujimoto, R., Motoyoshi, M., & Fujishima, M. (2013). 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. In 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 [6656291] https://doi.org/10.1109/ISCDG.2013.6656291

1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. / Yodprasit, Uroschanit; Katayama, Kosuke; Fujimoto, Ryuichi; Motoyoshi, Mizuki; Fujishima, Minoru.

2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013. 2013. 6656291.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yodprasit, U, Katayama, K, Fujimoto, R, Motoyoshi, M & Fujishima, M 2013, 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. in 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013., 6656291, 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013, Dresden, Germany, 13/9/26. https://doi.org/10.1109/ISCDG.2013.6656291
Yodprasit U, Katayama K, Fujimoto R, Motoyoshi M, Fujishima M. 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. In 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013. 2013. 6656291 https://doi.org/10.1109/ISCDG.2013.6656291
Yodprasit, Uroschanit ; Katayama, Kosuke ; Fujimoto, Ryuichi ; Motoyoshi, Mizuki ; Fujishima, Minoru. / 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013. 2013.
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