1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

H. Kubosawa; H. Takahashi; S. Ando; Y. Asada; A. Asato; A. Suga; M. Kimura; N. Higaki; H. Miyake; T. Sato; H. Anbutsu; T. Tsuda; T. Yoshimura; I. Amano; M. Kai; S. Mitarai

1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

H. Kubosawa^*, H. Takahashi, S. Ando, Y. Asada, A. Asato, A. Suga, M. Kimura, N. Higaki, H. Miyake, T. Sato, H. Anbutsu, T. Tsuda, T. Yoshimura, I. Amano, M. Kai, S. Mitarai

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

Original language	English
Pages (from-to)	290-291
Number of pages	2
Journal	Unknown Journal
Publication status	Published - 1998

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

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title = "1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications",

abstract = "A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.",

author = "H. Kubosawa and H. Takahashi and S. Ando and Y. Asada and A. Asato and A. Suga and M. Kimura and N. Higaki and H. Miyake and T. Sato and H. Anbutsu and T. Tsuda and T. Yoshimura and I. Amano and M. Kai and S. Mitarai",

year = "1998",

language = "English",

pages = "290--291",

journal = "Nuclear Physics A",

issn = "0375-9474",

publisher = "Elsevier",

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T1 - 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

AU - Kubosawa, H.

AU - Takahashi, H.

AU - Ando, S.

AU - Asada, Y.

AU - Asato, A.

AU - Suga, A.

AU - Kimura, M.

AU - Higaki, N.

AU - Miyake, H.

AU - Sato, T.

AU - Anbutsu, H.

AU - Tsuda, T.

AU - Yoshimura, T.

AU - Amano, I.

AU - Kai, M.

AU - Mitarai, S.

PY - 1998

Y1 - 1998

N2 - A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

AB - A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

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JO - Nuclear Physics A

JF - Nuclear Physics A

ER -

1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

Abstract

ASJC Scopus subject areas

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