120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Masanori Hayashikoshi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara

120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

Yasushi Terada^*, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	Anon
Publisher	Publ by IEEE
Pages	136-137, 315
Volume	32
Publication status	Published - 1989
Externally published	Yes
Event	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA Duration: 1989 Feb 15 → 1989 Feb 17

Other

Other	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
City	New York, NY, USA
Period	89/2/15 → 89/2/17

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Terada, Y, Kobayashi, K, Nakayama, T, Hayashikoshi, M, Miyawaki, Y, Ajika, N, Arima, H, Matsukawa, T & Yoshihara, T 1989, 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 32, Publ by IEEE, pp. 136-137, 315, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989), New York, NY, USA, 89/2/15.

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abstract = "A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.",

author = "Yasushi Terada and Kazuo Kobayashi and Takeshi Nakayama and Masanori Hayashikoshi and Yoshikazu Miyawaki and Natsuo Ajika and Hideaki Arima and Takayuki Matsukawa and Tsutomu Yoshihara",

year = "1989",

language = "English",

volume = "32",

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editor = "Anon",

booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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T1 - 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

AU - Terada, Yasushi

AU - Kobayashi, Kazuo

AU - Nakayama, Takeshi

AU - Hayashikoshi, Masanori

AU - Miyawaki, Yoshikazu

AU - Ajika, Natsuo

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

PY - 1989

Y1 - 1989

N2 - A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

AB - A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

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M3 - Conference contribution

AN - SCOPUS:0024908026

VL - 32

SP - 136-137, 315

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Anon, null

PB - Publ by IEEE

T2 - IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)

Y2 - 15 February 1989 through 17 February 1989

ER -

120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

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ASJC Scopus subject areas

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