120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
PublisherPubl by IEEE
Pages136-137, 315
Volume32
Publication statusPublished - 1989
Externally publishedYes
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 1989 Feb 151989 Feb 17

Other

OtherIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
CityNew York, NY, USA
Period89/2/1589/2/17

Fingerprint

PROM
Data storage equipment
Polysilicon
Masks
Clocks
Metals

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Terada, Y., Kobayashi, K., Nakayama, T., Hayashikoshi, M., Miyawaki, Y., Ajika, N., ... Yoshihara, T. (1989). 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. In Anon (Ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 32, pp. 136-137, 315). Publ by IEEE.

120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. / Terada, Yasushi; Kobayashi, Kazuo; Nakayama, Takeshi; Hayashikoshi, Masanori; Miyawaki, Yoshikazu; Ajika, Natsuo; Arima, Hideaki; Matsukawa, Takayuki; Yoshihara, Tsutomu.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Anon. Vol. 32 Publ by IEEE, 1989. p. 136-137, 315.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Terada, Y, Kobayashi, K, Nakayama, T, Hayashikoshi, M, Miyawaki, Y, Ajika, N, Arima, H, Matsukawa, T & Yoshihara, T 1989, 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 32, Publ by IEEE, pp. 136-137, 315, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989), New York, NY, USA, 89/2/15.
Terada Y, Kobayashi K, Nakayama T, Hayashikoshi M, Miyawaki Y, Ajika N et al. 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. In Anon, editor, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 32. Publ by IEEE. 1989. p. 136-137, 315
Terada, Yasushi ; Kobayashi, Kazuo ; Nakayama, Takeshi ; Hayashikoshi, Masanori ; Miyawaki, Yoshikazu ; Ajika, Natsuo ; Arima, Hideaki ; Matsukawa, Takayuki ; Yoshihara, Tsutomu. / 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / Anon. Vol. 32 Publ by IEEE, 1989. pp. 136-137, 315
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