120-ns 128K × 8-bit/64K × 16-bit CMOS EEPROMs

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A 1-Mb CMOS full-featured EEPROM using a 1.0-μm triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mb EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient error checking and correction scheme is developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8 × 8.0 μm2, and the chip size is 7.73 × 11.83 mm2. The device is organized as either 128K × 8 or 64K × 16 by via-hole mask options. A 256-byte/128-word-page-mode programming is implemented.

Original languageEnglish
Pages (from-to)1244-1249
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number5
DOIs
Publication statusPublished - 1989 Oct
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Terada, Y., Kobayashi, K., Nakayama, T., Hayashikoshi, M., Miyawaki, Y., Ajika, N., Arima, H., Matsukawa, T., & Yoshihara, T. (1989). 120-ns 128K × 8-bit/64K × 16-bit CMOS EEPROMs. IEEE Journal of Solid-State Circuits, 24(5), 1244-1249. https://doi.org/10.1109/JSSC.1989.572588