12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Hiroshi Fuketa*, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Fingerprint

Dive into the research topics of '12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics'. Together they form a unique fingerprint.

Engineering & Materials Science