1.2GFLOPS neural network chip exhibiting fast convergence

Yoshikazu Kondo, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hirofumi Shinohara, Hakuro Mori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
PublisherPubl by IEEE
Pages218-219
Number of pages2
ISBN (Print)0780318455
Publication statusPublished - 1994 Jan 1
EventProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1994 Feb 161994 Feb 18

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference

Other

OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period94/2/1694/2/18

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kondo, Y., Koshiba, Y., Arima, Y., Murasaki, M., Yamada, T., Amishiro, H., Shinohara, H., & Mori, H. (1994). 1.2GFLOPS neural network chip exhibiting fast convergence. In Anon (Ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 218-219). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Publ by IEEE.