TY - GEN
T1 - 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO
AU - Hirairi, Koji
AU - Okuma, Yasuyuki
AU - Fuketa, Hiroshi
AU - Yasufuku, Tadashi
AU - Takamiya, Makoto
AU - Nomura, Masahiro
AU - Shinohara, Hirofumi
AU - Sakurai, Takayasu
PY - 2012/5/11
Y1 - 2012/5/11
N2 - Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.
AB - Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.
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U2 - 10.1109/ISSCC.2012.6177102
DO - 10.1109/ISSCC.2012.6177102
M3 - Conference contribution
AN - SCOPUS:84860653751
SN - 9781467303736
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 486
EP - 487
BT - 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
T2 - 59th International Solid-State Circuits Conference, ISSCC 2012
Y2 - 19 February 2012 through 23 February 2012
ER -