13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Citations (Scopus)

Abstract

Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.

Original languageEnglish
Title of host publication2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Pages486-487
Number of pages2
DOIs
Publication statusPublished - 2012 May 11
Event59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
Duration: 2012 Feb 192012 Feb 23

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume55
ISSN (Print)0193-6530

Other

Other59th International Solid-State Circuits Conference, ISSCC 2012
CountryUnited States
CitySan Francisco, CA
Period12/2/1912/2/23

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2012). 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 486-487). [6177102] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). https://doi.org/10.1109/ISSCC.2012.6177102