13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Koji Hirairi; Yasuyuki Okuma; Hiroshi Fuketa; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1109/ISSCC.2012.6177102

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

34 Citations (Scopus)

Abstract

Scaling power supply voltages (V _DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V _DD, adaptive V _DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V _DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.

Original language	English
Title of host publication	2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Pages	486-487
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2012.6177102
Publication status	Published - 2012 May 11
Externally published	Yes
Event	59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States Duration: 2012 Feb 19 → 2012 Feb 23

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	55
ISSN (Print)	0193-6530

Other

Other	59th International Solid-State Circuits Conference, ISSCC 2012
Country/Territory	United States
City	San Francisco, CA
Period	12/2/19 → 12/2/23

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/ISSCC.2012.6177102

Cite this

Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2012). 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 486-487). [6177102] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). https://doi.org/10.1109/ISSCC.2012.6177102

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. / Hirairi, Koji; Okuma, Yasuyuki; Fuketa, Hiroshi; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 486-487 6177102 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hirairi, K, Okuma, Y, Fuketa, H, Yasufuku, T, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2012, 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. in 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers., 6177102, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 55, pp. 486-487, 59th International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, United States, 12/2/19. https://doi.org/10.1109/ISSCC.2012.6177102

Hirairi K, Okuma Y, Fuketa H, Yasufuku T, Takamiya M, Nomura M et al. 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 486-487. 6177102. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2012.6177102

Hirairi, Koji ; Okuma, Yasuyuki ; Fuketa, Hiroshi ; Yasufuku, Tadashi ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. pp. 486-487 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.",

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AU - Yasufuku, Tadashi

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

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AB - Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.

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13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

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