130-mm2, 256-Mbit NAND flash with shallow trench isolation technology

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)

Abstract

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm2, which realizes a 130-mm2, 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput.

Original languageEnglish
Pages (from-to)1536-1543
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume34
Issue number11
DOIs
Publication statusPublished - 1999 Nov 1
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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