14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.

Original languageEnglish
Title of host publicationRSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013
Pages235-237
Number of pages3
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013 - Austin, TX, United States
Duration: 2013 Jan 202013 Jan 23

Other

Other2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013
CountryUnited States
CityAustin, TX
Period13/1/2013/1/23

Fingerprint

Bandwidth
Energy dissipation
Capacitors
Feedback
MOS capacitors
Metals
Transceivers
Capacitance
Topology
Oxides
Networks (circuits)
Electric potential

Keywords

  • amplifier array
  • CMOS
  • DC offset canceller
  • limiting amplifiers

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Communication

Cite this

Takano, K., Fujimoto, R., Motoyoshi, M., Katayama, K., & Fujishima, M. (2013). 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. In RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013 (pp. 235-237). [6486699] https://doi.org/10.1109/RWS.2013.6486699

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. / Takano, Kyoya; Fujimoto, Ryuichi; Motoyoshi, Mizuki; Katayama, Kosuke; Fujishima, Minoru.

RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013. 2013. p. 235-237 6486699.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takano, K, Fujimoto, R, Motoyoshi, M, Katayama, K & Fujishima, M 2013, 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. in RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013., 6486699, pp. 235-237, 2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013, Austin, TX, United States, 13/1/20. https://doi.org/10.1109/RWS.2013.6486699
Takano K, Fujimoto R, Motoyoshi M, Katayama K, Fujishima M. 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. In RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013. 2013. p. 235-237. 6486699 https://doi.org/10.1109/RWS.2013.6486699
Takano, Kyoya ; Fujimoto, Ryuichi ; Motoyoshi, Mizuki ; Katayama, Kosuke ; Fujishima, Minoru. / 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013. 2013. pp. 235-237
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