14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.

Original languageEnglish
Title of host publication2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 - RWW 2013
Pages135-137
Number of pages3
DOIs
Publication statusPublished - 2013 Apr 15
Event2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013 - Austin, TX, United States
Duration: 2013 Jan 212013 Jan 23

Publication series

Name2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 - RWW 2013

Other

Other2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013
CountryUnited States
CityAustin, TX
Period13/1/2113/1/23

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Keywords

  • CMOS
  • DC offset canceller
  • amplifier array
  • limiting amplifiers

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Takano, K., Fujimoto, R., Motoyoshi, M., Katayama, K., & Fujishima, M. (2013). 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. In 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 - RWW 2013 (pp. 135-137). [6489457] (2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 - RWW 2013). https://doi.org/10.1109/SiRF.2013.6489457