14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications

Dajiang Zhou, Shihao Wang, Heming Sun, Jianbin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, the latest high-efficiency video coding standard (H.265/HEVC) greatly enhances the feasibility of 8K by doubling the compression ratio. Implementation of such codecs is a challenge, owing to ultra-high throughput requirements and increased complexity per pixel. The former corresponds to up to 10b/pixel, 7680×4320pixels/frame and 120fps - 80× larger than 1080p HD. The latter comes from the new features of HEVC relative to its predecessor H.264/AVC. The most challenging of them is the enlarged and highly variable-size coding/prediction/transform units (CU/PU/TU), which significantly increase: 1) the requirement for on-chip memory as pipeline buffers, 2) the difficulty in maintianing pipeline utilization, and 3) the complexity of inverse transforms (IT). This paper presents an HEVC decoder chip supporting 8K Ultra HD, featuring a 16pixel/cycle true-variable-block-size system pipeline. The pipeline: 1) saves on-chip memory with a novel block-in-block-out (BIBO) queue system and a parameter delivery network, and 2) allows high design efficiency and utilization of processing components through local synchronization. Key optimizations at the component level are also presented.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages266-268
Number of pages3
Volume59
ISBN (Print)9781467394666
DOIs
Publication statusPublished - 2016 Feb 23
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: 2016 Jan 312016 Feb 4

Other

Other63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period16/1/3116/2/4

Fingerprint

Pipelines
Pixels
Data storage equipment
Inverse transforms
Image coding
Synchronization
Buffers
Throughput
Mathematical transformations
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., ... Goto, S. (2016). 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 59, pp. 266-268). [7418009] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2016.7418009

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. / Zhou, Dajiang; Wang, Shihao; Sun, Heming; Zhou, Jianbin; Zhu, Jiayi; Zhao, Yijin; Zhou, Jinjia; Zhang, Shuping; Kimura, Shinji; Yoshimura, Takeshi; Goto, Satoshi.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 59 Institute of Electrical and Electronics Engineers Inc., 2016. p. 266-268 7418009.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhou, D, Wang, S, Sun, H, Zhou, J, Zhu, J, Zhao, Y, Zhou, J, Zhang, S, Kimura, S, Yoshimura, T & Goto, S 2016, 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 59, 7418009, Institute of Electrical and Electronics Engineers Inc., pp. 266-268, 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, United States, 16/1/31. https://doi.org/10.1109/ISSCC.2016.7418009
Zhou D, Wang S, Sun H, Zhou J, Zhu J, Zhao Y et al. 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 59. Institute of Electrical and Electronics Engineers Inc. 2016. p. 266-268. 7418009 https://doi.org/10.1109/ISSCC.2016.7418009
Zhou, Dajiang ; Wang, Shihao ; Sun, Heming ; Zhou, Jianbin ; Zhu, Jiayi ; Zhao, Yijin ; Zhou, Jinjia ; Zhang, Shuping ; Kimura, Shinji ; Yoshimura, Takeshi ; Goto, Satoshi. / 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 59 Institute of Electrical and Electronics Engineers Inc., 2016. pp. 266-268
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