16Mb DRAM/SOI technologies for sub-1V operation

T. Oashi, T. Eimori, F. Morishita, T. Iwamatsu, Y. Yamaguchi, F. Okuda, K. Shimomura, H. Shimano, N. Sakashita, K. Arimoto, Y. Inoue, S. Komori, M. Inuishi, T. Nishimura, H. Miyoshi

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET's, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1V.

Original languageEnglish
Pages (from-to)609-612
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1996 Dec 1
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1996 Dec 81996 Dec 11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Fingerprint Dive into the research topics of '16Mb DRAM/SOI technologies for sub-1V operation'. Together they form a unique fingerprint.

  • Cite this

    Oashi, T., Eimori, T., Morishita, F., Iwamatsu, T., Yamaguchi, Y., Okuda, F., Shimomura, K., Shimano, H., Sakashita, N., Arimoto, K., Inoue, Y., Komori, S., Inuishi, M., Nishimura, T., & Miyoshi, H. (1996). 16Mb DRAM/SOI technologies for sub-1V operation. Technical Digest - International Electron Devices Meeting, 609-612.