16Mb DRAM/SOI Technologies for Sub-1V Operation

T. Oashi, T. Eimori, F. Morishita, T. Iwamatsu, Y. Yamaguchi, F. Okuda, K. Shimomura*, H. Shimano, N. Sakashita, K. Arimoto, Y. Inoue, S. Komori, M. Inuishi, T. Nishimura, H. Miyoshi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Citations (Scopus)

Abstract

Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET’s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.

Original languageEnglish
Pages (from-to)609-612
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1996 Dec 81996 Dec 11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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