16Mb DRAM/SOI technologies for sub-1V operation

T. Oashi, T. Eimori, F. Morishita, T. Iwamatsu, Y. Yamaguchi, F. Okuda, K. Shimomura, H. Shimano, N. Sakashita, K. Arimoto, Y. Inoue, S. Komori, Masahide Inuishi, T. Nishimura, H. Miyoshi

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET's, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1V.

Original languageEnglish
Pages (from-to)609-612
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1996
Externally publishedYes

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Oashi, T., Eimori, T., Morishita, F., Iwamatsu, T., Yamaguchi, Y., Okuda, F., Shimomura, K., Shimano, H., Sakashita, N., Arimoto, K., Inoue, Y., Komori, S., Inuishi, M., Nishimura, T., & Miyoshi, H. (1996). 16Mb DRAM/SOI technologies for sub-1V operation. Unknown Journal, 609-612.