18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

Original languageEnglish
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
PublisherIEEE
Pages204-207
Number of pages4
Publication statusPublished - 1985
Externally publishedYes

Fingerprint

ram
Random access storage
very large scale integration
floating
central processing units
chips
Speech processing
Fast Fourier transforms
fast Fourier transformations
format
dynamic range
Hardware
CMOS
hardware
coding
requirements
cycles

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics

Cite this

Yamauchi, H., Kaneko, T., Kobayashi, T., Iwata, A., & Ono, S. (1985). 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (pp. 204-207). IEEE.

18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. / Yamauchi, Hironori; Kaneko, Takao; Kobayashi, Tsutomu; Iwata, Atsushi; Ono, Sadayasu.

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, 1985. p. 204-207.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yamauchi, H, Kaneko, T, Kobayashi, T, Iwata, A & Ono, S 1985, 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. in ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, pp. 204-207.
Yamauchi H, Kaneko T, Kobayashi T, Iwata A, Ono S. 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE. 1985. p. 204-207
Yamauchi, Hironori ; Kaneko, Takao ; Kobayashi, Tsutomu ; Iwata, Atsushi ; Ono, Sadayasu. / 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, 1985. pp. 204-207
@inproceedings{be58adaf27cb41598eeb1462b9ce8c22,
title = "18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.",
abstract = "A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.",
author = "Hironori Yamauchi and Takao Kaneko and Tsutomu Kobayashi and Atsushi Iwata and Sadayasu Ono",
year = "1985",
language = "English",
pages = "204--207",
booktitle = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",
publisher = "IEEE",

}

TY - GEN

T1 - 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

AU - Yamauchi, Hironori

AU - Kaneko, Takao

AU - Kobayashi, Tsutomu

AU - Iwata, Atsushi

AU - Ono, Sadayasu

PY - 1985

Y1 - 1985

N2 - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

AB - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

UR - http://www.scopus.com/inward/record.url?scp=0022245510&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022245510&partnerID=8YFLogxK

M3 - Conference contribution

SP - 204

EP - 207

BT - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

PB - IEEE

ER -