Abstract
A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.
| Original language | English |
|---|---|
| Title of host publication | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
| Publisher | IEEE |
| Pages | 204-207 |
| Number of pages | 4 |
| Publication status | Published - 1985 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering
- Acoustics and Ultrasonics
Cite this
18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. / Yamauchi, Hironori; Kaneko, Takao; Kobayashi, Tsutomu; Iwata, Atsushi; Ono, Sadayasu.
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, 1985. p. 204-207.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.
AU - Yamauchi, Hironori
AU - Kaneko, Takao
AU - Kobayashi, Tsutomu
AU - Iwata, Atsushi
AU - Ono, Sadayasu
PY - 1985
Y1 - 1985
N2 - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.
AB - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.
UR - http://www.scopus.com/inward/record.url?scp=0022245510&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0022245510&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0022245510
SP - 204
EP - 207
BT - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
PB - IEEE
ER -