18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Hironori Yamauchi; Takao Kaneko; Tsutomu Kobayashi; Atsushi Iwata; Sadayasu Ono

18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Hironori Yamauchi^*, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

Original language	English
Pages (from-to)	204-207
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication status	Published - 1985 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

Cite this

18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. / Yamauchi, Hironori; Kaneko, Takao; Kobayashi, Tsutomu; Iwata, Atsushi; Ono, Sadayasu.

In: ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 01.12.1985, p. 204-207.

Research output: Contribution to journal › Conference article › peer-review

@article{be58adaf27cb41598eeb1462b9ce8c22,

title = "18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.",

abstract = "A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.",

author = "Hironori Yamauchi and Takao Kaneko and Tsutomu Kobayashi and Atsushi Iwata and Sadayasu Ono",

year = "1985",

month = dec,

day = "1",

language = "English",

pages = "204--207",

journal = "Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing",

issn = "0736-7791",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

AU - Yamauchi, Hironori

AU - Kaneko, Takao

AU - Kobayashi, Tsutomu

AU - Iwata, Atsushi

AU - Ono, Sadayasu

PY - 1985/12/1

Y1 - 1985/12/1

N2 - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

AB - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

UR - http://www.scopus.com/inward/record.url?scp=0022245510&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022245510&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0022245510

SP - 204

EP - 207

JO - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing

JF - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing

SN - 0736-7791

ER -

18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Abstract

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this