18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Hironori Yamauchi; Takao Kaneko; Tsutomu Kobayashi; Atsushi Iwata; Sadayasu Ono

18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono

Research output: Contribution to journal › Conference article › peer-review

Abstract

A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

Original language	English
Pages (from-to)	204-207
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication status	Published - 1985 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

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18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM. / Yamauchi, Hironori; Kaneko, Takao; Kobayashi, Tsutomu; Iwata, Atsushi; Ono, Sadayasu.

In: ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 01.12.1985, p. 204-207.

Research output: Contribution to journal › Conference article › peer-review

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